lpc2468fet208 NXP Semiconductors, lpc2468fet208 Datasheet
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lpc2468fet208 Summary of contents
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... ISP/IAP, USB 2.0 device/host/OTG, external memory interface Rev. 02 — 16 October 2007 1. General description NXP Semiconductors designed the LPC2468 microcontroller around a 16-bit/32-bit ARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG and embedded trace. The LPC2468 has 512 kB of on-chip high-speed flash memory. This fl ...
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... NXP Semiconductors SRAM for general purpose DMA use also accessible by the USB SRAM data storage powered from the Real-Time Clock (RTC) power domain. I Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention. ...
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... Ordering information Type number Package Name LPC2468FBD208 LQFP208 LPC2468FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; body 15 15 LPC2468_2 Preliminary data sheet Description plastic low profile quad flat package; 208 leads; body 28 Rev. 02 — 16 October 2007 ...
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... NXP Semiconductors 4.1 Ordering options Table 2. Ordering options Type number Flash (kB) LPC2468FBD208 512 LPC2468FET208 512 LPC2468_2 Preliminary data sheet SRAM (kB) External Ethernet bus 98 Full 32-bit MII/ RMII 98 Full 32-bit MII/ RMII Rev. 02 — 16 October 2007 LPC2468 Fast communication chip ...
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... NXP Semiconductors 5. Block diagram LPC2468 P0, P1, P2, P3, P4 HIGH-SPEED GPI/O 160 PINS TOTAL AHB2 ETHERNET MII/RMII MAC WITH DMA EINT3 to EINT0 EXTERNAL INTERRUPTS P0 CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 MAT2/MAT3, TIMER2/TIMER3 2 MAT0, 3 MAT1 6 PWM0/PWM1 PWM0, PWM1 1 PCAP0, 2 PCAP1 LEGACY GPI/O P0 PINS TOTAL ...
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... PWM0[5]/DSR1 LPC2468_2 Preliminary data sheet 1 LPC2468FBD208 52 ball A1 index area LPC2468FET208 Transparent top view Pin Symbol V 3 P1[0]/ENET_TXD0 SSIO P1[9]/ENET_RXD0 7 P1[14]/ENET_RX_ER P1[3]/ENET_TXD3/ 11 P4[15]/A15 MCICMD/PWM0[2] P1[11]/ENET_RXD2/ 15 P0[8]/I2STX_WS/ MCIDAT2/PWM0[6] MISO1/MAT2[2] Rev. 02 — ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 17 P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] Row B 1 P3[2]/ P1[1]/ENET_TXD1 6 9 P4[25]/ DD(3V3) 17 P2[0]/PWM1[1]/TXD1/ TRACECLK Row C 1 P3[13]/D13 2 5 P3[9]/ DD(3V3) 13 P0[7]/I2STX_CLK/SCK1 14 /MAT2[ DD(3V3) Row D 1 TRST 2 5 P3[11]/D11 6 9 P1[2]/ENET_TXD2/ ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row H 1 P0[23]/AD0[0]/ 2 I2SRX_CLK/CAP3[ SSIO Row J 1 P3[6]/ P0[16]/RXD1/ 15 SSEL0/SSEL Row K 1 VREF 2 14 P4[22]/A22/ 15 TXD2/MISO1 Row L 1 P3[7]/ Row M 1 P3[15]/D15 2 14 P4[6]/A6 15 Row N 1 ALARM 2 14 P2[12]/EINT2/ 15 MCIDAT2/I2STX_WS ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol 13 P2[17]/RAS 14 17 P4[20]/A20/ SDA2/SCK1 Row T 1 P0[27]/SDA0 SSIO 9 P1[24]/USB_RX_DM1/ 10 PWM1[5]/MOSI0 13 P1[28]/USB_SCL1/ 14 PCAP1[0]/MAT0[0] 17 P2[11]/EINT1/ MCIDAT1/I2STX_CLK Row U 1 USB_D P2[23]/DYCS3/ 6 CAP3[1]/SSEL0 9 P4[0]/ DD(3V3) 17 P4[16]/A16 6.2 Pin description Table 4 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[3]/RXD0 204 D6 [1] P0[4]/ 168 B12 I2SRX_CLK/ RD2/CAP2[0] [1] P0[5]/ 166 C12 I2SRX_WS/ TD2/CAP2[1] [1] P0[6]/ 164 D13 I2SRX_SDA/ SSEL1/MAT2[0] [1] P0[7]/ 162 C13 I2STX_CLK/ SCK1/MAT2[1] [1] P0[8]/ 160 A15 I2STX_WS/ MISO1/MAT2[2] [1] P0[9]/ 158 C14 I2STX_SDA/ MOSI1/MAT2[3] [1] P0[10]/TXD2/ 98 T15 SDA2/MAT3[0] [1] P0[11]/RXD2/ 100 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [2] P0[12 USB_PPWR2/ MISO1/AD0[6] [2] P0[13 USB_UP_LED2/ MOSI1/AD0[7] [1] P0[14 USB_HSTEN2/ USB_CONNECT2/ SSEL1 [1] P0[15]/TXD1/ 128 J16 SCK0/SCK [1] P0[16]/RXD1/ 130 J14 SSEL0/SSEL [1] P0[17]/CTS1/ 126 K17 MISO0/MISO [1] P0[18]/DCD1/ 124 K15 MOSI0/MOSI [1] P0[19]/DSR1/ 122 L17 MCICLK/SDA1 [1] P0[20]/DTR1/ 120 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P0[21]/RI1/ 118 M16 MCIPWR/RD1 [1] P0[22]/RTS1/ 116 N17 MCIDAT0/TD1 [2] P0[23]/AD0[0 I2SRX_CLK/ CAP3[0] [2] P0[24]/AD0[1 I2SRX_WS/ CAP3[1] [2] P0[25]/AD0[2 I2SRX_SDA/ TXD3 [2][3] P0[26]/AD0[3 AOUT/RXD3 [4] P0[27]/SDA0 50 T1 [4] P0[28]/SCL0 48 R3 [5] P0[29]/USB_D [5] P0[30]/USB_D [5] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[0]/ 196 A3 ENET_TXD0 [1] P1[1]/ 194 B5 ENET_TXD1 [1] P1[2]/ 185 D9 ENET_TXD2/ MCICLK/ PWM0[1] [1] P1[3]/ 177 A10 ENET_TXD3/ MCICMD/ PWM0[2] [1] P1[4]/ 192 A5 ENET_TX_EN [1] P1[5]/ 156 A17 ENET_TX_ER/ MCIPWR/ PWM0[3] [1] P1[6]/ 171 B11 ENET_TX_CLK/ MCIDAT0/ PWM0[4] [1] P1[7]/ 153 D14 ENET_COL/ MCIDAT1/ PWM0[5] [1] P1[8]/ 190 C7 ENET_CRS_DV/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[13]/ 147 D16 ENET_RX_DV [1] P1[14]/ 184 A7 ENET_RX_ER [1] P1[15]/ 182 A8 ENET_REF_CLK/ ENET_RX_CLK [1] P1[16]/ 180 D10 ENET_MDC [1] P1[17]/ 178 A9 ENET_MDIO [1] P1[18 USB_UP_LED1/ PWM1[1]/ CAP1[0] [1] P1[19 USB_TX_E1/ USB_PPWR1/ CAP1[1] [1] P1[20 USB_TX_DP1/ PWM1[2]/SCK0 [1] P1[21 USB_TX_DM1/ PWM1[3]/SSEL0 [1] P1[22 USB_RCV1/ USB_PWRD1/ ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P1[24 USB_RX_DM1/ PWM1[5]/MOSI0 [1] P1[25]/ 80 T10 USB_LS1/ USB_HSTEN1/ MAT1[1] [1] P1[26]/ 82 R10 USB_SSPND1/ PWM1[6]/ CAP0[0] [1] P1[27]/ 88 T12 USB_INT1/ USB_OVRCR1/ CAP0[1] [1] P1[28]/ 90 T13 USB_SCL1/ PCAP1[0]/ MAT0[0] [1] P1[29]/ 92 U14 USB_SDA1/ PCAP1[1]/ MAT0[1] [2] P1[30 USB_PWRD2/ V /AD0[4] ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[1]/PWM1[2]/ 152 E14 RXD1/ PIPESTAT0 [1] P2[2]/PWM1[3]/ 150 D15 CTS1/ PIPESTAT1 [1] P2[3]/PWM1[4]/ 144 E16 DCD1/ PIPESTAT2 [1] P2[4]/PWM1[5]/ 142 D17 DSR1/ TRACESYNC [1] P2[5]/PWM1[6]/ 140 F16 DTR1/ TRACEPKT0 [1] P2[6]/PCAP1[0]/ 138 E17 RI1/TRACEPKT1 [1] P2[7]/RD2/ 136 G16 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [6] P2[11]/EINT1/ 108 T17 MCIDAT1/ I2STX_CLK [6] P2[12]/EINT2/ 106 N14 MCIDAT2/ I2STX_WS [6] P2[13]/EINT3/ 102 T16 MCIDAT3/ I2STX_SDA [6] P2[14]/CS2/ 91 R12 CAP2[0]/SDA1 [6] P2[15]/CS3/ 99 P13 CAP2[1]/SCL1 [1] P2[16]/CAS 87 R11 [1] P2[17]/RAS 95 R13 [1] P2[18 CLKOUT0 [1] P2[19 CLKOUT1 [1] P2[20]/DYCS0 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P2[23]/DYCS3 CAP3[1]/SSEL0 [1] P2[24 CKEOUT0 [1] P2[25 CKEOUT1 [1] P2[26 CKEOUT2/ MAT3[0]/MISO0 [1] P2[27 CKEOUT3/ MAT3[1]/MOSI0 [1] P2[28 DQMOUT0 [1] P2[29 DQMOUT1 [1] P2[30 DQMOUT2/ MAT3[2]/SDA2 [1] P2[31 DQMOUT3/ MAT3[3]/SCL2 P3[0] to P3[31] [1] P3[0]/D0 197 B4 [1] P3[1]/D1 201 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[5]/ [1] P3[6]/ [1] P3[7]/ [1] P3[8]/D8 191 D8 [1] P3[9]/D9 199 C5 [1] P3[10]/D10 205 B2 [1] P3[11]/D11 208 D5 [1] P3[12]/D12 1 D4 [1] P3[13]/D13 7 C1 [1] P3[14]/D14 21 H2 [1] P3[15]/D15 28 M1 [1] P3[16]/D16/ 137 F17 PWM0[1]/TXD1 [1] P3[17]/D17/ 143 F15 PWM0[2]/RXD1 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[20]/D20/ 167 A13 PWM0[5]/DSR1 [1] P3[21]/D21/ 175 C10 PWM0[6]/DTR1 [1] P3[22]/D22/ 195 C6 PCAP0[0]/RI1 [1] P3[23]/D23 CAP0[0]/ PCAP1[0] [1] P3[24]/D24 CAP0[1]/ PWM1[1] [1] P3[25]/D25 MAT0[0]/ PWM1[2] [1] P3[26]/D26 MAT0[1]/ PWM1[3] [1] P3[27]/D27/ 203 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P3[30]/D30 MAT1[1]/ RTS1 [1] P3[31]/D31 MAT1[2] P4[0] to P4[31] [1] P4[0]/ [1] P4[1]/A1 79 U10 [1] P4[2]/A2 83 T11 [1] P4[3]/A3 97 U16 [1] P4[4]/A4 103 R15 [1] P4[5]/A5 107 R16 [1] P4[6]/A6 113 M14 [1] P4[7]/A7 121 L16 [1] P4[8]/A8 127 J17 [1] P4[9]/A9 131 H17 [1] P4[10]/A10 135 G17 [1] P4[11]/A11 145 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[15]/A15 173 A11 [1] P4[16]/A16 101 U17 [1] P4[17]/A17 104 P14 [1] P4[18]/A18 105 P15 [1] P4[19]/A19 111 P16 [1] P4[20]/A20/ 109 R17 SDA2/SCK1 [1] P4[21]/A21/ 115 M15 SCL2/SSEL1 [1] P4[22]/A22/ 123 K14 TXD2/MISO1 [1] P4[23]/A23/ 129 J15 RXD2/MOSI1 [1] P4[24]/OE 183 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball [1] P4[29]/BLS3/ 176 B10 MAT2[1]/RXD3 [1] P4[30]/CS0 187 B7 [1] P4[31]/CS1 193 A4 [8] ALARM 37 N1 USB_D [1] DBGEN 9 F4 [1] TDO 2 D3 [1] TDI 4 C2 [1] TMS 6 E3 [1] TRST 8 D1 [1] TCK 10 E2 [1] RTCK 206 C3 [1] RSTOUT ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin Ball V 15, 60, G3, P6, DD(3V3) 71, 89, P8, U13, 112, P17, 125, K16, 146, C17, 165, B13, C9, 181, D7 [11] 198 NC 30, 117, J4, L14, [12] 141 G14 V 26, 86, H4, P11, DD(DCDC)(3V3) [13] 174 D11 [14 DDA [14] ...
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... NXP Semiconductors The LPC2468 implements two AHB buses in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM ...
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... NXP Semiconductors The LPC2468 provides a minimum of 100000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2468 includes a SRAM memory reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. ...
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... NXP Semiconductors 4.0 GB 3.75 GB 3.5 GB 3.0 GB 2.0 GB 1.0 GB 0.0 GB Fig 4. LPC2468 memory map 7.5 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority ...
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... NXP Semiconductors – Asynchronous page mode read – Programmable Wait States – Bus turnaround delay – Output enable and write enable delays – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices • ...
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... NXP Semiconductors • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • ...
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... NXP Semiconductors 7.10 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet fi ...
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... NXP Semiconductors – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. ...
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... NXP Semiconductors 7.11.2.1 Features • OHCI compliant. • Two downstream ports. • Supports per-port power switching. 7.11.3 USB OTG Controller USB OTG (On-The-Go supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals ...
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... NXP Semiconductors • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.13 10-bit ADC The LPC2468 contains one ADC single 10-bit successive approximation ADC with eight channels. 7.13.1 Features • 10-bit successive approximation ADC • ...
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... NXP Semiconductors • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). ...
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... NXP Semiconductors 7.18.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11 . • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. ...
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... NXP Semiconductors 2 The I S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave. 7.20.1 Features • ...
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... NXP Semiconductors 7.22 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2468. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specifi ...
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... NXP Semiconductors • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • ...
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... NXP Semiconductors 7.24.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator or programmable prescaler from APB clock. ...
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... NXP Semiconductors 7.25.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.25.2 PLL The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz. The input frequency is multiplied high frequency, then divided down to provide the actual clock used by the CPU and the USB block ...
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... NXP Semiconductors values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application ...
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... NXP Semiconductors 7.25.4.4 Power domains The LPC2468 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2468, I/O pads are powered by the 3 DD(DCDC)(3V3) the CPU and most of the peripherals. ...
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... NXP Semiconductors The second stage of low-voltage detection asserts Reset to inactivate the LPC2468 when the voltage on the V flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below which point the power-on reset circuitry maintains the overall Reset ...
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... NXP Semiconductors 7.26.5 External interrupt inputs The LPC2468 includes edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.26.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000 ...
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... NXP Semiconductors addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter supply voltage DD(DCDC)(3V3) (3 analog 3.3 V pad supply voltage DDA V input voltage on pin VBAT i(VBAT) V input voltage on pin VREF ...
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... NXP Semiconductors 9. Static characteristics Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (3.3 V) DD(3V3) V DC-to-DC converter DD(DCDC)(3V3) supply voltage (3 analog 3.3 V pad DDA supply voltage V input voltage on pin i(VBAT) VBAT V input voltage on pin ...
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... NXP Semiconductors Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I active mode DC-to-DC DD(DCDC)act(3V3) converter supply current (3 power-down mode DD(DCDC)pd(3V3) DC-to-DC converter supply current (3 active mode battery BATact supply current 2 I C-bus pins (P0[27] and P0[28]) ...
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... NXP Semiconductors Table 7. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V differential input DI sensitivity V differential common CM mode voltage range V single-ended receiver th(rs)se switching threshold voltage V LOW-level output OL voltage for low-/full-speed V HIGH-level output OH voltage (driven) for ...
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... NXP Semiconductors [1] Conditions 3.3 V. SSA DDA [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (E D [4] The integral non-linearity (E L(adj) appropriate adjustment of gain and offset errors. See [5] The offset error ( the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors AD0[y] Fig 6. Suggested ADC interface - LPC2468 AD0[y] pin LPC2468_2 Preliminary data sheet LPC2XXX 20 k SAMPLE Rev. 02 — 16 October 2007 LPC2468 Fast communication chip R vsi AD0[y] V EXT 002aac733 © NXP B.V. 2007. All rights reserved ...
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... NXP Semiconductors 10. Dynamic characteristics Table 9. Dynamic characteristics of USB pins (full-speed pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 10.1 Timing V 0 0.2V 0.2V 0.45 V Fig 7. External clock timing t PERIOD differential data lines Fig 8. Differential data-to-EOP transition skew and EOP width shifting edges SCK MOSI MISO Fig 9. MISO line set-up time in SSP Master mode LPC2468_2 Preliminary data sheet 0 0 ...
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... NXP Semiconductors 11. Application information 11.1 Suggested USB interface solutions LPC24XX Fig 10. LPC2468 USB interface on a self-powered device LPC24XX Fig 11. LPC2468 USB interface on a bus-powered device LPC2468_2 Preliminary data sheet V DD(3V3) USB_UP_LED USB_CONNECT soft-connect switch R1 1 BUS USB_D USB_D DD(3V3) ...
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... NXP Semiconductors RSTOUT USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D 1 USB_UP_LED1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D 2 USB_UP_LED2 Fig 12. LPC2468 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host LPC2468_2 Preliminary data sheet RESET_N ADR/PSW OE_N/INT_N ...
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... NXP Semiconductors RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1 LPC24XX USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1 Fig 13. LPC2468 USB OTG port configuration: VP_VM mode LPC2468_2 Preliminary data sheet V DD RESET_N OE_N/INT_N DAT_VP SE0_VM RCV ISP1301 ADR/PSW SPEED SUSPEND SCL SDA ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D 1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_UP_LED2 USB_CONNECT2 USB_D+2 USB_D 2 V BUS Fig 14. LPC2468 USB OTG port configuration: USB port 2 device, USB port 1 host LPC2468_2 Preliminary data sheet FLAGA ENA OUTA 5 V LM3526-L ...
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... NXP Semiconductors USB_UP_LED1 USB_D+1 USB_D 1 USB_PWRD1 USB_OVRCR1 USB_PPWR1 LPC24XX USB_PPWR2 USB_OVRCR2 USB_PWRD2 USB_D+2 USB_D 2 USB_UP_LED2 Fig 15. LPC2468 USB OTG port configuration: USB port 1 host, USB port 2 host LPC2468_2 Preliminary data sheet FLAGA ENA OUTA LM3526-L ...
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... NXP Semiconductors 12. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.6 0.4 OUTLINE ...
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... NXP Semiconductors 13. Abbreviations Table 11. Acronym ADC AHB AMBA APB ATX BLS BOD CAN DAC DCC DMA DSP EOP ETM GPIO IrDA JTAG MII PHY PLL PWM RMII SD/MMC SE0 SPI SSI SSP TTL UART USB LPC2468_2 Preliminary data sheet Acronym list ...
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... NXP Semiconductors 14. Revision history Table 12. Revision history Document ID Release date LPC2468_2 20071016 • Modifications: Incorrect character fonts have been replaced in figures 10, 11, 12, 13, 14 and 15. LPC2468_1 20070903 LPC2468_2 Preliminary data sheet Data sheet status Change notice Preliminary data sheet - Preliminary data sheet - Rev. 02 — ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional description . . . . . . . . . . . . . . . . . . 24 7.1 Architectural overview 7.2 On-chip flash programming memory . . . . . . . 25 7.3 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 26 7.4 Memory map 7.5 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 27 7.5.1 Interrupt sources 7.6 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 28 7 ...
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... NXP Semiconductors 15.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 15.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 16 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Fast communication chip Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...