r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 120

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
7.4.23
7.4.24
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 01F5h
Address 01F6h
The VLT0 register selects the voltage level of the input threshold values for ports P0 to P3. Bits VLT00 to
VLT07 are used to select the input threshold values among three voltage levels (0.35 VCC, 0.50 VCC, and 0.70
VCC) for every eight pins.
The VLT1 register selects the voltage level of the input threshold values for ports P4_2 to P4_7, and P6. Bits
VLT10 and VLT11, VLT14 and VLT15 are used to select the input threshold values among three voltage levels
(0.35 VCC, 0.50 VCC, and 0.70 VCC).
Symbol
Symbol
Symbol
Symbol
VLT00
VLT01
VLT02
VLT03
VLT04
VLT05
VLT06
VLT07
VLT10
VLT11
VLT14
VLT15
Bit
Bit
Input Threshold Control Register 0 (VLT0)
Input Threshold Control Register 1 (VLT1)
—
—
—
—
VLT07
b7
b7
—
0
0
P0 input level select bit
P1 input level select bit
P2 input level select bit
P3 input level select bit
P4_2 to P4_7 input level select bit
Reserved bits
P6 input level select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
VLT06
b6
b6
—
0
0
Bit Name
Bit Name
VLT05
VLT15
b5
b5
0
0
VLT04
VLT14
b4
b4
0
0
b1 b0
b3 b2
b5 b4
b7 b6
b1 b0
Set to 0.
b5 b4
VLT03
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
0 0: 0.50 × VCC
0 1: 0.35 × VCC
1 0: 0.70 × VCC
1 1: Do not set.
b3
b3
—
0
0
VLT02
b2
b2
—
0
0
Function
Function
VLT01
VLT11
b1
b1
0
0
VLT00
VLT10
b0
b0
0
0
Page 88 of 740
7. I/O Ports
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—