r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 130

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Table 7.31
X: 0 or 1
Notes:
Table 7.32
X: 0 or 1
Notes:
Register PD3
Register
Setting
Setting
Value
Value
Bit
Bit
1.
2.
3.
1.
2.
3.
4.
Output drive capacity high by setting the DRR06 bit in the DRR0 register to 1.
Output drive capacity high by setting the DRR07 bit in the DRR0 register to 1.
Pulled up by setting the PU06 bit in the PUR0 register to 1.
N-channel open-drain output by setting the CSOS bit in the SSMR2 register to 1 (N-channel open-drain output).
Pulled up by setting the PU07 bit in the PUR0 register to 1.
N-channel open-drain output by setting the SOOS bit in the SSMR2 register to 1 (N-channel open-drain output) and setting the BIDE bit in the
SSMR2 register to 0 (standard mode).
N-channel open-drain output by setting the NCH bit in the U2C0 register to 1.
PD3_4
PD3_3
PD3
0
1
0
X
X
X
0
0
X
0
0
0
1
0
0
X
X
0
X
0
SSUIICSR
SSMR2
IICSEL
1
0
0
0
0
0
1
1
0
0
0
CSS
Port P3_3/INT3/TRCCLK/SCS/CTS2/RTS2/IVCMP3
Port P3_4/TRCIOC/SSI/RXD2/SCL2/TXD2/SDA2/IVREF3
X
X
X
X
0
0
X
X
X
X
X
0
0
0
0
0
1
0
1
0
0
0
INT3SEL
SSI output
INTSR
1
X
X
0
X
X
X
X
X
X
Association between
Modes and I/O Pins .)
Communication Unit
(Refer to Table 25.4
Synchronous Serial
control
Communication
0
0
0
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
0
0
INT3EN
INTEN
SSI input
X
X
X
X
X
X
X
1
1
control
0
0
0
0
1
0
0
0
0
0
0
Other than 10b
TRCCLKSEL
TRBRCSR
1
X
X
X
1
X
X
X
X
TRCPSR1
Other than
Other than
Other than
Other than
2
0
0
X
X
X
X
X
TRCIOC
010b
010b
010b
010b
SEL
1
1
1
X
X
X
X
X
0
X
X
X
0
X
X
X
X
X
X
X
X
X
0
0
0
RXD2
Other
Other
Other
Other
X
X
X
X
Other
1
0
0
than
than
than
than
than
SEL
01b
01b
01b
01b
01b
2
X
X
X
1
X
X
X
X
X
TRCCR1
X
X
X
X
0
1
1
TCK
U2SR0
X
X
X
X
X
X
X
X
1
0
Other than
Other than
Other than
Other than
Other than
Other than
Other than
X
X
2
0
0
TXD2
010b
010b
010b
010b
010b
010b
010b
0
X
X
X
1
X
X
X
X
X
SEL
X
X
1
1
1
CTS2SEL0
U2SR1
0
X
X
0
0
0
0
0
0
X
X
1
1
0
2
X
X
X
X
X
X
X
0
0
1
0
X
U2MR
SMD
1
X
X
X
X
X
X
X
1
0
1
1
X
X
X
X
X
Other than
Other than
X
2
X
X
X
X
X
X
X
X
0
0
1
0
1
0
0
U2MR
SMD
000b
000b
U2SMR INTCMP
X
X
X
X
X
X
X
1
IICM
X
X
X
X
X
X
X
1
X
1
X
0
X
X
X
X
X
CRS CRD INT3CP0
X
X
X
X
X
X
X
0
1
INT3
CP0
U2CO
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
0
0
Refer to Table
Refer to Table
7.52 TRCIOC
7.52 TRCIOC
Pin Setting
Pin Setting
Timer RC
INTCMP
Setting
—
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
1
Input port
Output port
INT3 input
TRCCLK input
SCS input
SCS output
CTS2 input
RTS2 output
Comparator B3
input (IVCMP3)
Page 98 of 740
Input port
Output port
TRCIOC
input
TRCIOC
output
SSI input
SSI output
RXD2 input
SCL2 input/
output
TXD2
output
SDA2 input/
output
Comparator B3
reference
voltage input
(IVREF3)
Function
7. I/O Ports
Function
(1)
(2, 4)
(2, 4)
(2)
(2, 4)
(1)
(1)
(1)
(1)
(2)
(2, 3)
(1)
(1)
(2, 3)
(2)
(2)
(1)
(1)