r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 142

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
8.
The bus cycles differ when accessing ROM, RAM, DTC vector area, DTC control data and when accessing SFR.
Table 8.1 lists Bus Cycles by Access Area of R8C/34M Group.
ROM, RAM, DTC vector area, DTC control data and SFR are connected to the CPU by an 8-bit bus. When accessing
in word (16-bit) units, these areas are accessed twice in 8-bit units.
Table 8.2 shows Access Units and Bus Operations.
However, only the following SFRs are connected with the 16-bit bus:
Interrupts: Each interrupt control register
Timer RC: Registers TRC, TRCGRA, TRCGRB, TRCGRC, and TRCGRD
Timer RD: Registers TRDi (i = 0, 1), TRDGRAi, TRDGRBi, TRDGRCi, and TRDGRDi
SSU: Registers SSTDR, SSTDRH, SSRDR, and SSRDRH
UART2: Registers U2MR, U2BRG, U2TB, U2C0, U2C1, U2RB, U2SMR5, U2SMR4, U2SMR3, U2SMR2,
A/D converter: Registers AD0, AD1, AD2, AD3, AD4, AD5, AD6, AD7, ADMOD, ADINSEL, ADCON0,
D/A converter: Registers DA0 and DA1
Address match interrupt: Registers RMAD0, AIER0, RMAD1, and AIER1
Therefore, they are accessed once in 16-bit units. The bus operation is the same as “Area: SFR, Data flash, Even
address Byte Access” in Table 8.2 Access Units and Bus Operations, and 16-bit data is accessed at a time.
Table 8.1
Table 8.2
SFR/Data flash
Program ROM/RAM
Bus
Even address
Even address
Odd address
Word access
Odd address
Word access
Byte access
Byte access
and U2SMR
Area
and ADCON1
Bus Cycles by Access Area of R8C/34M Group
Access Units and Bus Operations
Access Area
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
SFR, Data flash
Even
Odd
Data
Data
Even
Odd
2 cycles of CPU clock
1 cycle of CPU clock
Even + 1
Odd + 1
Data
Data
Data
Data
Bus Cycle
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
CPU clock
Address
Data
DTC vector area, DTC control data
ROM (program ROM), RAM,
Even
Even
Odd
Odd
Data
Data
Data
Data
Even + 1
Odd + 1
Page 110 of 740
Data
Data
8. Bus