r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 149

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
9.2.4
Notes:
9.2.5
b7-b0 32 MHz frequency correction data is stored.
1. Set bits OCD1 to OCD0 to 00b before the MCU enters stop mode, high-speed on-chip oscillator mode, or low-
2. If the OCD2 bit is set to 1 (on-chip oscillator clock selected), the CM14 bit is set to 0 (low-speed on-chip oscillator
3. The OCD2 bit is automatically set to 1 (on-chip oscillator clock selected) if XIN clock oscillation stop is detected
4. The OCD3 bit is enabled when the OCD0 bit is set to 1 (oscillation stop detection function enabled). In addition,
5. The OCD3 bit remains 0 (XIN clock oscillates) if bits OCD1 to OCD0 are set to 00b.
6. Refer to Figure 9.9 Procedure for Switching to XIN Clock when XIN Clock Re-Oscillates after Oscillation
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 000Ch
Address 0015h
speed on-chip oscillator mode (XIN clock stops).
on).
while bits OCD1 to OCD0 are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains
unchanged even when set to 0 (XIN clock selected).
the OCD3 bit cannot be used to confirm whether the XIN clock oscillation is stable.
Stop is Detected for the switching procedure when the XIN clock re-oscillates after detecting oscillation stop.
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting the OCD register.
Symbol
Symbol
The frequency can be adjusted by transferring this value to the FRA3 register and by
transferring the correction value in the FRA6 register to the FRA1 register.
Symbol
OCD0 Oscillation stop detection enable bit
OCD1 Oscillation stop detection interrupt
OCD2 System clock select bit
OCD3 Clock monitor bit
Bit
Bit
Oscillation Stop Detection Register (OCD)
High-Speed On-Chip Oscillator Control Register 7 (FRA7)
—
—
—
—
b7
b7
—
—
0
enable bit
Reserved bits
b6
b6
—
—
0
Bit Name
(4, 5)
b5
—
b5
—
0
(3)
When shipping
Function
b4
b4
—
—
0
(6)
0: Oscillation stop detection function disabled
1: Oscillation stop detection function enabled
0: Disabled
1: Enabled
0: XIN clock selected
1: On-chip oscillator clock selected
0: XIN clock oscillates
1: XIN clock stops
Set to 0.
OCD3
b3
b3
—
0
OCD2
(1)
b2
b2
—
1
Function
OCD1
(6)
b1
b1
—
0
9. Clock Generation Circuit
OCD0
b0
b0
—
0
(2)
R/W
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R
(1)
R/W
R/W
R/W
R/W
R/W
R