r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 177

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
11.1.2
11.1.2.1
11.1.2.2
11.1.2.3
11.1.2.4
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
An undefined instruction interrupt is generated when the UND instruction is executed.
An overflow interrupt is generated when the O flag is set to 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that set the O flag are as follows:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.
A BRK interrupt is generated when the BRK instruction is executed.
An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers 0 to
63 can be specified with the INT instruction. Because some software interrupt numbers are assigned to
peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by
executing the INT instruction.
For software interrupt numbers 0 to 31, the U flag is saved on the stack during instruction execution and the U
flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is restored from the stack
when returning from the interrupt routine. For software interrupt numbers 32 to 63, the U flag does not change
state during instruction execution, and the selected SP is used.
Software Interrupts
Undefined Instruction Interrupt
Overflow Interrupt
BRK Interrupt
INT Instruction Interrupt
Page 145 of 740
11. Interrupts