r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 185

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 11.3
11.3.4
Address Bus
CPU Clock
Data Bus
The following describes an interrupt sequence which is performed from when an interrupt request is
acknowledged until the interrupt routine is executed.
When an interrupt request is generated while an instruction is being executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following cycle.
However, for the SMOVB, SMOVF, SSTR, or RMPA instruction, if an interrupt request is generated while the
instruction is being executed, the MCU suspends the instruction to start the interrupt sequence. The interrupt
sequence is performed as indicated below.
Figure 11.3 shows the Time Required for Executing Interrupt Sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading address
(2) The FLG register is saved to a temporary register
(3) The I, D and U flags in the FLG register are set as follows:
(4) The CPU internal temporary register
(5) The PC is saved on the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, instructions are executed from the starting address of the interrupt
routine.
Notes:
Note:
WR
RD
The indeterminate state depends on the instruction queue buffer.
A read cycle occurs when the instruction queue buffer is ready to acknowledge instructions.
00000h. The IR bit for the corresponding interrupt is set to 0 (no interrupt requested).
sequence.
The I flag is set to 0 (interrupts disabled).
The D flag is set to 0 (single-step interrupt disabled).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is
executed.
1. These registers cannot be accessed by the user.
2. Refer to 11.7 Timer RC Interrupt, Timer RD Interrupt, Synchronous Serial Communication Unit
Interrupt Sequence
Interrupt, I
Interrupt Request Sources) for the IR bit operations of the timer RC Interrupt, timer RD Interrupt,
Synchronous Serial Communication unit Interrupt, and the I
1
Time Required for Executing Interrupt Sequence
2
Address
0000h
information
Interrupt
3
2
C bus Interface Interrupt, and Flash Memory Interrupt (Interrupts with Multiple
4
5
Undefined
Undefined
Undefined
6
7
(1)
is saved on the stack.
8
SP-2 SP-1
9
contents
SP-2
10
(1)
contents
SP-1
in the CPU immediately before entering the interrupt
SP-4
11
contents
SP-4
12
SP-3
contents
SP-3
2
13
C bus Interface Interrupt.
VEC
14
contents
VEC
15
VEC+1
contents
VEC+1
16
17
(2)
VEC+2
contents
VEC+2
18
Page 153 of 740
11. Interrupts
19
PC
20