r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 197

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
11.6
Table 11.8
Notes:
Table 11.9
• Instruction with 2-byte operation code
• Instruction with 1-byte operation code
ADD.B:S
OR.B:S
STNZ
CMP.B:S
JMPS
MOV.B:S
Instructions other than above
Address match interrupt 0
Address match interrupt 1
Address Match Interrupt Source Address Match Interrupt Enable Bit Address Match Interrupt Register
An address match interrupt request is generated immediately before execution of the instruction at the address
indicated by the RMADi register (i = 0 or 1). This interrupt is used as a break function by the debugger. When the
on-chip debugger is used, do not set an address match interrupt (registers AIER0, AIER1, RMAD0, and RMAD1,
and fixed vector tables) in the user system.
Set the starting address of any instruction in the RMADi register (i = 0 or 1). The AIERi0 bit in the AIERi register
can be used to select enable or disable the interrupt. The address match interrupt is not affected by the I flag and
IPL.
The PC value (refer to 11.3.7 Saving Registers) which is saved on the stack when an address match interrupt
request is acknowledged varies depending on the instruction at the address indicated by the RMADi register. (The
appropriate return address is not saved on the stack.) When returning from the address match interrupt, follow one
of the following means:
•
•
Table 11.8 lists the PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged.
1. Refer to 11.3.7 Saving Registers .
2. Operation code: Refer to the R8C/Tiny Series Software Manual (REJ09B0001).
Rewrite the contents of the stack and use the REIT instruction to return.
Use an instruction such as POP to restore the stack to its previous state before the interrupt request was
acknowledged. Then use a jump instruction to return.
Address Match Interrupt
#IMM8,dest SUB.B:S
#IMM8,dest MOV.B:S #IMM8,dest STZ
#IMM8,dest STZX
#IMM8,dest PUSHM
#IMM8
#IMM,dest (however, dest = A0 or A1)
Correspondence Between Address Match Interrupt Sources and Associated Registers
PC Value Saved on Stack When Address Match Interrupt Request is Acknowledged
Address Indicated by RMADi Register (i = 0 or 1)
Chapter 4. Instruction Code/Number of Cycles contains diagrams showing
operation code below each syntax. Operation code is shown in the bold frame in
the diagrams.
JSRS
AIER00
AIER10
#IMM8,dest AND.B:S
#IMM81,#IMM82,dest
src
#IMM8
(2)
(2)
POPM
#IMM8,dest
#IMM8,dest
dest
RMAD0
RMAD1
Address indicated by
RMADi register + 2
Address indicated by
RMADi register + 1
PC Value Saved
Page 165 of 740
11. Interrupts
(1)