r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 217

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
14.2.7
Note:
1. The OFS2 register is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a
Bits WDTRCS0 and WDTRCS1
(Watchdog Timer Refresh Acknowledgement Period Set Bit)
Bit
b0
b1
b2
b3
b4
b5
b6
b7
After Reset
program.
Do not write additions to the OFS2 register. If the block including the OFS2 register is erased, the OFS2 register
is set to FFh.
When blank products are shipped, the OFS2 register is set to FFh. It is set to the written value after written by the
user.
When factory-programming products are shipped, the value of the OFS2 register is the value programmed by the
user.
For a setting example of the OFS2 register, refer to 13.3.1 Setting Example of Option Function Select Area.
Assuming that the period from when the watchdog timer starts counting until it underflows is 100%, the refresh
acknowledgement period for the watchdog timer can be selected.
For details, refer to 14.3.1.1 Refresh Acknowledgement Period.
Address 0FFDBh
Symbol
WDTUFS0 Watchdog timer underflow period set bit
WDTUFS1
WDTRCS0 Watchdog timer refresh acknowledgement period
WDTRCS1
Symbol
Option Function Select Register 2 (OFS2)
Bit
—
—
—
—
b7
—
set bit
Reserved bits
b6
—
b5
—
Bit Name
User Setting Value
b4
—
WDTRCS1 WDTRCS0 WDTUFS1 WDTUFS0
b3
(1)
b1 b0
b3 b2
Set to 1.
0 0: 03FFh
0 1: 0FFFh
1 0: 1FFFh
1 1: 3FFFh
0 0: 25%
0 1: 50%
1 0: 75%
1 1: 100%
b2
Function
b1
14. Watchdog Timer
b0
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R/W
R/W
R/W
R/W
R/W
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