r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 220

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
14.3.3
Table 14.3
Notes:
Count source
Count operation
Period
Watchdog timer
initialization conditions
Count start conditions
Count stop condition
Operation at underflow
Registers, bits
1. The WDTON bit cannot be changed by a program. To set this bit, write 0 to bit 0 of address 0FFFFh
2. Even if 0 is written to the CSPROINI bit in the OFS register, the CSPRO bit is set to 1. The
3. Write the WDTR register during the count operation of the watchdog timer.
The count source for the watchdog timer is the low-speed on-chip oscillator clock for the watchdog timer when
count source protection mode is enabled. If the CPU clock stops when a program is out of control, the clock can
still be supplied to the watchdog timer.
Table 14.3 lists the Watchdog Timer Specifications (Count Source Protection Mode Enabled).
with a flash programmer.
CSPROINI bit cannot be changed by a program. To set this bit, write 0 to bit 7 of address 0FFFFh
with a flash programmer.
Count Source Protection Mode Enabled
Item
Watchdog Timer Specifications (Count Source Protection Mode Enabled)
Low-speed on-chip oscillator clock
Decrement
m: Value set by bits WDTUFS0 and WDTUFS1 in the OFS2 register
Example:
The period is approximately 8.2 ms when:
- The on-chip oscillator clock for the watchdog timer is set to 125 kHz.
- Bits WDTUFS1 to WDTUFS0 are set to 00b (03FFh).
• Reset
• Write 00h and then FFh to the WDTR register
• Underflow
The operation of the watchdog timer after a reset is selected by
the WDTON bit
• When the WDTON bit is set to 1 (watchdog timer is stopped after reset).
• When the WDTON bit is set to 0 (watchdog timer starts automatically after
None (Count does not stop even in wait mode and stop mode once it starts.)
Watchdog timer reset (Refer to 5.5 Watchdog Timer Reset. )
• When the CSPPRO bit in the CSPR register is set to 1 (count source
Low-speed on-chip oscillator clock for the watchdog timer
The watchdog timer and prescaler are stopped after a reset and
start counting when the WDTS register is written to.
reset).
The watchdog timer and prescaler start counting automatically after a reset.
protection mode enabled)
- The low-speed on-chip oscillator for the watchdog timer is on.
- The PM12 bit in the PM1 register is set to 1 (watchdog timer reset when the
watchdog timer underflows).
Count value of watchdog timer (m)
(1)
in the OFS register (address 0FFFFh).
(2)
, the following are set automatically:
Specification
(3)
14. Watchdog Timer
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