r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 223

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
15.2.1
Notes:
15.2.2
Note:
1. This bit is valid when the MODE bit is 1 (repeat mode).
2. Settings of bits SAMOD and DAMOD are invalid for the repeat area.
3. Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
1. When the DTBLS register is set to 00h, the block size is 256 bytes.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b7 to b0
Address Refer to Table 15.4 Control Data Allocation Addresses .
Address Refer to Table 15.4 Control Data Allocation Addresses .
Symbol
Symbol
Bit
RPTSEL Repeat area select bit
DAMOD Destination address control bit
SAMOD Source address control bit
RPTINT Repeat mode interrupt enable bit
Symbol
MODE
CHNE
Bit
Bit
DTC Control Register j (DTCCRj) (j = 0 to 23)
DTC Block Size Register j (DTBLSj) (j = 0 to 23)
—
—
These bits specify the size of the data block to be transferred by one
activation.
b7
b7
—
—
X
X
Transfer mode select bit
Chain transfer enable bit
Reserved bits
b6
b6
—
—
X
X
Bit Name
RPTINT
b5
b5
—
X
X
(1)
(3)
(2)
CHNE
Function
b4
b4
—
X
X
(2)
(1)
DAMOD SAMOD RPTSEL
0: Normal mode
1: Repeat mode
0: Transfer destination is the repeat area.
1: Transfer source is the repeat area.
0: Fixed
1: Incremented
0: Fixed
1: Incremented
0: Chain transfers disabled
1: Chain transfers enabled
0: Interrupt generation disabled
1: Interrupt generation enabled
Set to 0.
b3
b3
—
X
X
b2
b2
—
X
X
Function
b1
b1
—
X
X
MODE
b0
X
b0
—
Setting Range
00h to FFh
X
Page 191 of 740
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15. DTC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W