r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 224

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r5f21346mnfp

Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
r5f21346mnfp#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
15.2.3
Note:
15.2.4
Note:
15.2.5
15.2.6
b7 to b0 This register value is reloaded to the DTCCT register in repeat mode.
b7 to b0 These bits specify the number of times of DTC data transfers.
b15 to b0 These bits specify a transfer destination address for data transfer.
1. When the DTCCT register is set to 00h, the number of transfer times is 256. Each time the DTC is activated, the
1. Set the initial value for the DTCCT register.
b15 to b0
After Reset
After Reset
After Reset
After Reset
After Reset
After Reset
Bit
Bit
Address Refer to Table 15.4 Control Data Allocation Addresses .
Address Refer to Table 15.4 Control Data Allocation Addresses .
Address Refer to Table 15.4 Control Data Allocation Addresses .
Address Refer to Table 15.4 Control Data Allocation Addresses .
Bit
Bit
DTCCT register is decremented by 1.
Symbol
Symbol
Symbol
Symbol
Symbol
Symbol
Bit
Bit
Bit
Bit
Bit
Bit
DTC Transfer Count Register j (DTCCTj) (j = 0 to 23)
DTC Transfer Count Reload Register j (DTRLDj) (j = 0 to 23)
DTC Source Address Register j (DTSARj) (j = 0 to 23)
DTC Destination Address Register j (DTDARj) (j = 0 to 23)
These bits specify a transfer source address for data transfer.
b15
b15
b7
b7
b7
b7
X
X
X
X
X
X
b14
b14
b6
b6
b6
b6
X
X
X
X
X
X
b13
b13
b5
b5
b5
b5
X
X
X
X
X
X
Function
Function
Function
Function
b12
b12
b4
b4
b4
b4
X
X
X
X
X
X
b11
b11
b3
b3
b3
b3
X
X
X
X
X
X
b10
b10
b2
b2
b2
b2
X
X
X
X
X
X
b1
b1
b1
b9
b1
b9
X
X
X
X
X
X
0000h to FFFFh
0000h to FFFFh
00h to FFh
Setting Range
Setting Range
00h to FFh
Setting Range
b0
b0
b0
b8
b0
b8
X
Setting Range
X
X
X
X
X
(1)
Page 192 of 740
(1)
15. DTC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

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