r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 226

no-image

r5f21346mnfp

Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r5f21346mnfp#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
15.2.8
Note:
1.
NMIF Bit (Non-Maskable Interrupt Generation Bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0080h
This bit is set to 0 when the read result is 1 and 0 is written to the same bit. This bit remains
unchanged even if the read result is 0 and 0 is written to the same bit. This bit remains unchanged if
1 is written to it.
The DTCTL register controls DTC activation when a non-maskable interrupt (an interrupt by the watchdog
timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated.
The NMIF bit is set to 1 when a watchdog timer interrupt, an oscillation stop detection interrupt, a voltage
monitor 1 interrupt, or a voltage monitor 2 interrupt is generated.
When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is
generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed.
When an interrupt source is the watchdog timer, wait for the following cycles before writing 0 to the NMIF bit:
If the WDTC7 bit in the WDTC register is set to 0 (divide-by-16 using the prescaler), wait for 16 cycles of the
CPU clock after the interrupt source is generated.
If the WDTC7 bit is set to 1 (divide-by-128 using the prescaler), wait for 128 cycles of the CPU clock after the
interrupt source is generated.
When an interrupt source is oscillation stop detection, set to the OCD1 bit in the OCD register to 0 (oscillation
stop detection interrupt disabled) before writing 0 to the NMIF bit.
Symbol
Symbol
Bit
NMIF
DTC Activation Control Register (DTCTL)
b7
0
Reserved bit
Non-maskable interrupt generation
bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
(1)
b6
0
Bit Name
b5
0
b4
0
Set to 0.
0: Non-maskable interrupts not generated
1: Non-maskable interrupts generated
b3
0
b2
0
Function
NMIF
b1
0
b0
0
Page 194 of 740
15. DTC
R/W
R/W
R/W

Related parts for r5f21346mnfp