r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 227

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
15.3
Figure 15.2
15.3.1
15.3.2
When the DTC is activated, control data is read from the DTC control data area to perform data transfers and
control data after data transfer is written back to the DTC control data area. Twenty-four sets of control data can
be stored in the DTC control data area, which allows 24 types of data transfers to be performed.
There are two transfer modes: normal mode and repeat mode. When the CHNE bit in the DTCCRj (j = 0 to 23)
register is set to 1 (chain transfers enabled), multiple control data is read and data transfers are continuously
performed by one activation source (chain transfers).
A transfer source address is specified by the 16-bit register DTSARj, and a transfer destination address is
specified by the 16-bit register DTDARj. The values in the registers DTSARj and DTDARj are separately fixed
or incremented according to the control data on completion of the data transfer.
The DTC is activated by an interrupt source. Figure 15.2 is a Block Diagram Showing Control of DTC
Activation Sources.
The interrupt sources to activate the DTC are selected with the DTCENi (i = 0 to 6) registers.
The DTC sets 0 (activation disabled) to the corresponding bit among bits DTCENi0 to DTCENi7 in the
DTCENi register during operation when the setting of data transfer (the first transfer in chain transfers) is either
of the following:
• Transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode
• Transfer causing the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1
If the data transfer setting is not either of the above and the activation source is an interrupt source for timer RC,
timer RD, or the flash memory, the DTC sets 0 to the interrupt source flag corresponding to the activation
source during operation.
Table 15.3 shows the DTC Activation Sources and Interrupt Source Flags for Setting to 0 during DTC
Operation.
If multiple activation sources are simultaneously generated, the DTC activation will be performed according to
the DTC activation source priority.
If multiple activation sources are simultaneously generated on completion of DTC operation, the next transfer
will be performed according to the priority.
DTC activation is not affected by the I flag or interrupt control register, unlike with interrupt request operation.
Therefore, even if interrupt requests cannot be acknowledged because interrupts are disabled, DTC activation
requests can be acknowledged. The IR bit in the interrupt control register does not change even when an
interrupt source to enable DTC activation is generated.
Peripheral function 1
Peripheral function 2
(timer RC, timer RD,
(interrupt generation enabled) in repeat mode
Function Description
flash memory)
Overview
Activation Sources
Block Diagram Showing Control of DTC Activation Sources
Set the interrupt source flag
in the status register to 0.
Peripheral interrupt
Peripheral interrupt
request
request
Select interrupt source or
DTC activation source
Interrupt controller
Clear control
DTCENi
Interrupt request
Select DTC activation or
interrupt generation.
Set the bit among bits DTCENi0 to
DTCENi7 (i = 0 to 6) to 0.
DTC activation
request
DTC
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15. DTC