r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 237

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r5f21346mnfp

Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
r5f21346mnfp#V0
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 15.11
Figure 15.12
15.3.8
Table 15.8
j = 0 to 23
X: 0 or 1
CPU clock
Address
Bits b3 to b0
in DTCCR
Register
00X0b
01X0b
10X0b
X001b
X101b
11X0b
0X11b
1X11b
The DTC requires five clock cycles to read control data allocated in the DTC control data area. The number of
clock cycles required to write back control data differs depending on the control data settings.
Figure 15.11 shows an Example of DTC Operation Timings and Figure 15.12 shows an Example of DTC
Operation Timings in Chain Transfers.
Table 15.8 shows the Specifications of Control Data Write-Back Operation.
CPU clock
Address
Used by CPU
Operation Timings
Operating
Specifications of Control Data Write-Back Operation
Normal
Repeat
Example of DTC Operation Timings
Example of DTC Operation Timings in Chain Transfers
Read vector
Mode
mode
mode
Used by CPU
Incremented
Incremented Incremented Written back Written back Written back Written back
Incremented
Repeat area
Read control data
Source
Fixed
Fixed
Fixed
Address Control
Read vector
Incremented Written back Written back
Incremented Written back Written back Written back Written back
Repeat area
Destination
Transfer data Write back control data
Read
Fixed
Fixed
Fixed
Read control data
Write
Written back Written back
Written back Written back Written back
Written back Written back Written back
Written back Written back
Written back Written back Written back Written back
Register
DTCCTj
Control Data to be Written Back
Transfer data Write back control data
Read
Read control data
Register
DTRLDj
Write
Not written
Not written
Not written
Register
DTSARj
back
back
back
Read
Transfer data Write back control data
Write
Written back
Written back
Not written
Not written
Not written
DTDARj
Register
back
back
back
Used by CPU
Page 205 of 740
Number of
Cycles
Used by CPU
Clock
15. DTC
1
2
2
3
2
3
2
3

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