r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 238

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
15.3.9
Table 15.9
Notes:
Table 15.10
Operation
Data read
Data write
Vector Read
1. For the number of clock cycles required for data read/write, refer to Table 15.10 Number of Clock
2. For the number of clock cycles required for control data write-back, refer to Table 15.8
Table 15.9 shows the Operations Following DTC Activation and Required Number of Cycles for each
operation.
Table 15.10 shows the Number of Clock Cycles Required for Data Transfers.
Data is transferred as described below, when the DTBLSj (j = 0 to 23) register = N,
(1) When N = 2n (even), two-byte transfers are performed n times.
(2) When N = 2n + 1 (odd), two-byte transfers are performed n times followed by one time of one-byte
From Tables 15.9 and 15.10, the total number of required execution cycles can be obtained by the following
formula:
Number of required execution cycles = 1 + Σ[formula A] + 2
Σ: Sum of the cycles for the number of transfer times performed by one activation source ([the number of
transfer times for which CHNE is set to 1] + 1)
(1) For N = 2n (even)
(2) For N = 2n+1 (odd)
To read data from or write data to the register that to be accessed in 16-bit units, set an even value of 2 or greater
to the DTBLSj (j = 0 to 23) register.
The DTC performs accesses in 16-bit units.
Cycles Required for Data Transfers .
Specifications of Control Data Write-Back Operation .
1
transfer.
Formula A = J + n • SK2 + n • SL2
Formula A = J + n • SK2 + 1 • SK1 + n • SL2 + 1 • SL1
J: Number of cycles required to read control data (5 cycles) + number of cycles required to write back control data
Number of DTC Execution Cycles
1-byte SK1
2-byte SK2
1-byte SL1
2-byte SL2
Transfers
Unit of
Operations Following DTC Activation and Required Number of Cycles
Number of Clock Cycles Required for Data Transfers
(During DTC Transfers) Internal ROM
Address
Read
Even
Internal RAM
1
1
5
Control Data
1
1
Address
Odd
2
2
Write-back
(Note 2)
(Program ROM)
—
—
1
2
(Data flash)
Data Read
(Note 1)
Internal
ROM
—
—
2
4
Address
Even
(Word Access)
2
2
SFR
Data Write
2
2
(Note 1)
Address
Odd
4
4
Access)
(Byte
SFR
2
4
2
4
Internal Operation
(DTC control data area)
Address
Even
Page 206 of 740
1
1
1
SFR
1
1
Address
15. DTC
Odd
2
2