r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 265

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
18.2.7
Note:
18.2.8
b7 to b0 Timer mode
1. The values of registers TRBPR and TRBSC are reloaded to the counter alternately and counted.
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Address 010Eh
Address 0181h
When the TSTOP bit in the TRBCR register is set to 1, the TRBPR register is set to FFh.
The TRBRCSR register selects which pin is assigned to the timer RB and timer RC I/O. To use the I/O pin for
timer RB and timer RC, set this register.
Set the TRBOSEL0 bit before setting the timer RB associated registers. Set bits TRCCLKSEL0 and
TRCCLKSEL1 before setting the timer RC associated registers. Also, do not change the setting values of the
TRBOSEL0 bit during timer RB operation. Do not change the setting values of bits TRCCLKSEL0 and
TRCCLKSEL1 during timer RC operation.
Symbol
Symbol
TRCCLKSEL0 TRCCLK pin select bit
TRCCLKSEL1
Programmable waveform generation
mode
Programmable one-shot generation
mode
Programmable wait one-shot
generation mode
TRBOSEL0
Bit
Bit
Timer RB Primary Register (TRBPR)
Timer RB/RC Pin Select Register (TRBRCSR)
Symbol
—
—
—
—
—
b7
b7
—
—
1
0
TRBO pin select bit
Reserved bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Mode
b6
b6
—
—
1
0
TRCCLKSEL1 TRCCLKSEL0
Bit Name
b5
—
1
b5
0
Counts timer RB prescaler underflows
Counts timer RB prescaler underflows
Counts timer RB prescaler underflows
(one-shot width is counted)
Counts timer RB prescaler underflows
(wait period width is counted)
b4
—
1
b4
0
b3
—
1
0: P1_3 assigned
1: P3_1 assigned
Set to 0.
b5 b4
Set to 0.
Function
0 0: TRCCLK pin not used
0 1: P1_4 assigned
1 0: P3_3 assigned
1 1: Do not set.
b3
—
0
b2
—
1
b2
—
0
b1
—
Function
1
(1)
00h to FFh
00h to FFh
00h to FFh
00h to FFh
b1
—
Setting Range
b0
0
—
1
TRBOSEL0
Page 233 of 740
b0
0
18. Timer RB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—