r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 286

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
19.2.5
Note:
Table 19.4
Notes:
Bit Symbol
1. The writing results are as follows:
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA and TRCGRB).
IMFB
IMFC
IMFD
IMFA
OVF
Address 0123h
•This bit is set to 0 when the read result is 1 and 0 is written to the same bit.
•This bit remains unchanged even if the read result is 0 and 0 is written to the same bit. (This bit remains 1 even
•This bit remains unchanged if 1 is written to it.
Symbol
if it is set to 1 from 0 after reading, and writing 0.)
Symbol
Bit
IMFC
IMFD
IMFA
IMFB
OVF
Timer RC Status Register (TRCSR)
—
—
—
TRCIOA pin input edge
TRCIOB pin input edge
TRCIOC pin input edge
TRCIOD pin input edge
When the TRC register overflows.
Source for Setting Bit of Each Flag to 1
Input capture Function
OVF
b7
0
Input capture / compare match flag A
Input capture / compare match flag B
Input capture / compare match flag C
Input capture / compare match flag D
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
Overflow flag
b6
—
1
Bit Name
Timer Mode
(1)
(1)
(1)
(1)
b5
—
1
When the values of the registers TRC and TRCGRA match.
When the values of the registers TRC and TRCGRB match.
When the values of the registers TRC and TRCGRC match.
When the values of the registers TRC and TRCGRD match.
Output Compare Function
b4
—
1
IMFD
[Source for setting this bit to 0]
Write 0 after read
[Source for setting this bit to 1]
Refer to Table 19.4 Source for Setting Bit of
Each Flag to 1 .
[Source for setting this bit to 0]
Write 0 after read
[Source for setting this bit to 1]
Refer to Table 19.4 Source for Setting Bit of
Each Flag to 1 .
b3
0
IMFC
b2
0
PWM Mode
(1)
(1)
Function
.
.
IMFB
b1
0
IMFA
b0
0
PWM2 Mode
Page 254 of 740
(2)
(2)
19. Timer RC
R/W
R/W
R/W
R/W
R/W
R/W
—