r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 321

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Table 19.13
j = A, B, or C
Count source
Count operation
PWM waveform
Count start conditions
Count stop conditions
Interrupt request
generation timing
TRCIOA/TRCTRG pin
function
TRCIOB pin function
TRCIOC and TRCIOD pin
functions
INT0 pin function
Read from timer
Write to timer
Selectable functions
Item
Specifications of PWM2 Mode
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
External signal (rising edge) input to TRCCLK pin
Increment TRC register
PWM period: 1/fk × (m + 1) (no TRCTRG input)
Active level width: 1/fk × (n - p)
Wait time from count start or trigger: 1/fk × (p + 1)
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 00b (TRCTRG trigger
• Bits TCEG1 to TCEG0 in the TRCCR2 register are set to 01b, 10b, or 11b (TRCTRG
• 0 (count stops) is written to the TSTART bit in the TRCMR register while the CSEL bit in
• The count stops due to a compare match with TRCGRA while the CSEL bit in the
• Compare match (contents of TRC and TRCGRj registers match)
• The TRC register overflows
Programmable I/O port or TRCTRG input
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRC register.
The TRC register can be written to.
• External trigger and valid edge selection
• Buffer operation (Refer to 19.3.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 19.3.4 Forced Cutoff of Pulse
• Digital filter (Refer to 19.3.3 Digital Filter .)
• A/D trigger generation
disabled) or the CSEL bit in the TRCCR2 register is set to 0 (count continues).
1 (count starts) is written to the TSTART bit in the TRCMR register.
trigger enabled) and the TSTART bit in the TRCMR register is set to 1 (count starts).
A trigger is input to the TRCTRG pin
the TRCCR2 register is set to 0 or 1.
The TRCIOB pin outputs the initial level in accordance with the value of the TOB bit in
the TRCCR1 register. The TRC register retains the value before count stops.
TRCCR2 register is set to 1
The TRCIOB pin outputs the initial level. The TRC register retains the value before
count stops if the CCLR bit in the TRCCR1 register is set to 0. The TRC register is set
to 0000h if the CCLR bit in the TRCCR1 register is set to 1.
The edge or edges of the signal input to the TRCTRG pin can be used as the PWM
output trigger: rising edge, falling edge, or both rising and falling edges
Output .)
fk: Count source frequency
m: TRCGRA register setting value
n: TRCGRB register setting value
p: TRCGRC register setting value
TRCIOB output
TRCTRG input
m+1
n+1
p+1
n-p
Specification
(TRCTRG: Rising edge, active level is “H”)
n+1
p+1
n-p
Page 289 of 740
19. Timer RC