r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 333

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
20.2
Figure 20.2
20.2.1
Table 20.3
i = 0 or 1
Note:
f1, f2, f4, f8, f32
fOCO40M
fOCO-F
fC2
External signal input
to TRDCLK pin
1. The count source fOCO40M can be used with VCC = 2.7 to 5.5 V.
TRDCLK/
TRDIOA0
Count Source
The count source selection method is the same in all modes. However, fC2 cannot be selected in PWM, reset
synchronous PWM, complementary PWM, or PWM3 mode. The external clock cannot be selected in PWM3
mode.
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation
clock of timer RD (refer to Table 20.1 Timer RD Operation Clocks).
When selecting fOCO40M or fOCO-F for the count source, set the FRA00 bit in the FRA0 register to 1 (high-
speed on-chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi (i = 0 or 1) register to 110b
(fOCO40M) or 111b (fOCO-F).
Common Items for Multiple Modes
Count Sources
(1)
Count Source Selection
Block Diagram of Count Source
STCLK = 1
STCLK = 0
fOCO40M
fOCO-F
fC2
f32
f1
f2
f4
f8
The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator
frequency).
Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).
Bits TCK2 to TCK0 in the TRDCRi register is set to 111b (fOCO-F).
Bits TCK2 to TCK0 in the TRDCRi register is set to 101b (TRDCLKi input or fC2)
The ITCLKi bit in the TRDECR register is set to 1 (fC2)
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
ITCLK0, ITCLK1: Bits in TRDECR register
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
ITCLKi = 1
ITCLKi = 0
TRDIOA0 I/O or programmable I/O port
CKEG1 to CKEG0
Valid edge
selected
= 011b
= 100b
= 110b
= 010b
= 111b
= 001b
TCK2 to TCK0
= 000b
= 101b
Selection
Count source
TRDi register
Page 301 of 740
20. Timer RD