r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 336

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 20.5
20.2.3
• Bits IOA2 to IOA0 in the TRDIORA0 register are set to 100b.
• Bits CMD1 to CMD0 in the TRDFCR register are set to 00b.
The above applies under the following conditions:
• The SYNC bit in the TRDMR register is set to 1 (synchronous operation).
• Bits CCLR2 to CCLR0 in the TRDCR0 register are set to 001b (set the TRD0 register to 0000h in input capture).
The TRD1 register is synchronized with the TRD0 register.
• Synchronous preset
• Synchronous clear
The PWM 3 bit in the TRDFCR register is set to 1.
Bits CCLR2 to CCLR0 in the TRDCR1 register are set to 011b (set the TRD1 register to 0000h synchronizing with
the TRD0 register).
When the SYNC bit in the TRDMR register is set to 1 (synchronous operation), the data is written to both the
TRD0 and TRD1 registers after writing to the TRDi register.
When the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi register are
set to 011b (synchronous clear), the TRD0 register is set to 0000h at the same time as the TRD1 register is set
to 0000h.
Also, when the SYNC bit in the TRDMR register is set to 1 and bits CCLR2 to CCLR0 in the TRDCRi
register are set to 011b (synchronous clear), the TRD1 register is set to 0000h at the same time as the TRD0
register is set to 0000h.
TRDIOA0 input
TRD0 register
TRD1 register
Synchronous Operation
Value in
Value in
Synchronous Operation
n
n
n writing
n is set
n is set
Set to 0000h with TRD0 register
Set to 0000h by input capture
(Input capture at the rising edge of the TRDIOA0 input)
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20. Timer RD