r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 355

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Table 20.7
i = 0 or 1, j = A, B, C, or D
Count sources
Count operations
Count period
Waveform output timing
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1 to
TRDIOD1 pin functions
INT0 pin function
Read from timer
Write to timer
Selectable functions
Item
Output Compare Function Specifications
f1, f2, f4, f8, f32, fC2, fOCO40M, fOCO-F
External signal input to the TRDCLK pin (valid edge selected by a program)
Increment
• When bits CCLR2 to CCLR0 in the TRDCRi register are set to 000b (free-running
• Bits CCLR1 to CCLR0 in the TRDCRi register are set to 01b or 10b (set the TRDi
Compare match
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register when the
• When the CSELi bit in the TRDSTR register is set to 0, the count stops at the
• Compare match (The content of the TRDi register matches content of the TRDGRji
• TRDi register overflows
Programmable I/O port, output-compare output, or TRDCLK (external clock) input
Programmable I/O port or output-compare output (Selectable by pin)
Programmable I/O port, pulse output forced cutoff signal input, or INT0 interrupt input
The count value can be read by reading the TRDi register.
• When the SYNC bit in the TRDMR register is set to 0 (timer RD0 and timer RD1
• When the SYNC bit in the TRDMR register is set to 1 (timer RD0 and timer RD1
• Output-compare output pin selection
• Output level at the compare match selection
• Initial output level selected
• Timing for setting the TRDi register to 0000h
• Buffer operation (Refer to 20.2.2 Buffer Operation. )
• Synchronous operation (Refer to 20.2.3 Synchronous Operation. )
• Changing output pins for registers TRDGRCi and TRDGRDi
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse Output Forced
• Timer RD can be used as the internal timer without output.
• A/D trigger generation
operation).
1/fk × 65536 fk: Frequency of count source
register to 0000h at the compare match in the TRDGRji register).
Frequency of count source x (n+1)
n: Setting value in the TRDGRji register
CSELi bit in the TRDSTR register is set to 1.
The output compare output pin holds output level before the count stops.
compare match in the TRDGRAi register.
The output compare output pin holds level after output change by the compare
match.
register.)
operate independently).
Data can be written to the TRDi register.
operate synchronously).
Data can be written to both the TRD0 and TRD1 registers by writing to the TRDi
register.
Either 1 pin or multiple pins among TRDIOAi, TRDIOBi, TRDIOCi, or TRDIODi.
“L” output, “H” output, or output level inverted
Set the level at period from the count start to the compare match.
Overflow or compare match in the TRDGRAi register
The TRDGRCi register can be used as output control of the TRDIOAi pin and the
TRDGRDi register can be used as output control of the TRDIOBi pin.
Cutoff. )
Specification
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20. Timer RD