r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 363

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
20.4.11 Timer RD Control Register i (TRDCRi) (i = 0 or 1) in Output Compare
Notes:
1. Enabled when the ITCLKi bit in the TRDECR register is set to 0 (TRDCLK input) and the STCLK bit in the
2. Enabled when the ITCLKi bit in the TRDECR register is set to 1 (fC2) in timer mode.
3. Enabled when bits TCK2 to TCK0 are set to 101b (TRDCLK input or fC2), the ITCLKi bit in the TRDECR is set to
4. This setting is enabled when the SYNC bit in the TRDMR register is set to 1 (registers TRD0 and TRD1 operate
5. To select fOCO-F, set it to the clock frequency higher than the CPU clock frequency.
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0140h (TRDCR0), 0150h (TRDCR1)
TRDFCR register is 1 (external clock input enabled).
0 (TRDCLK input), and the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
synchronously).
Symbol
Symbol
CKEG0 External clock edge select bit
CKEG1
CCLR0 TRDi counter clear select bit
CCLR1
CCLR2
Bit
TCK0
TCK1
TCK2
Function
CCLR2
b7
0
Count source select bit
CCLR1
b6
0
Bit Name
CCLR0
b5
0
CKEG1
(3)
b4
0
b2 b1 b0
b4 b3
b7 b6 b5
0 0 0: f1
0 0 1: f2
0 1 0: f4
0 1 1: f8
1 0 0: f32
1 0 1: TRDCLK input
1 1 0: fOCO40M
1 1 1: fOCO-F
0 0: Count at the rising edge
0 1: Count at the falling edge
1 0: Count at both edges
1 1: Do not set.
0 0 0: Disable clear (free-running operation)
0 0 1: Clear by compare match with the TRDGRAi
0 1 0: Clear by compare match with the TRDGRBi
0 1 1: Synchronous clear (clear simultaneously with
1 0 0: Do not set.
1 0 1: Clear by compare match with the TRDGRCi
1 1 0: Clear by compare match with the TRDGRDi
1 1 1: Do not set.
CKEG0
b3
0
register
register
other timer RDi counter)
register
register
TCK2
(5)
b2
0
(1)
Function
or fC2
TCK1
b1
0
(2)
(4)
TCK0
b0
0
Page 331 of 740
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W