r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 375

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Table 20.9
i = 0 or 1
j = B, C, or D
h = A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOA1 pin function
TRDIOB0, TRDIOC0, TRDIOD0,
TRDIOB1, TRDIOC1, TRDIOD1
pin functions
INT0 pin function
Read from timer
Write to timer
Selectable functions
PWM Mode Specifications
Item
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
Increment
PWM period: 1/fk x (m+1)
Programmable I/O port, pulse output forced cutoff signal input, or INT0
• One to three PWM output pins selectable with timer RDi
External signal input to the TRDCLK pin (valid edge selected by a
program)
Active level width: 1/fk x (m-n)
Inactive level width: 1/fk x (n+1)
1 (count starts) is written to the TSTARTi bit in the TRDSTR register.
• 0 (count stops) is written to the TSTARTi bit in the TRDSTR register
• When the CSELi bit in the TRDSTR register is set to 0, the count
• Compare match (The content of the TRDi register matches content of
• TRDi register overflows
Programmable I/O port or TRDCLK (external clock) input
Programmable I/O port
Programmable I/O port or pulse output (selectable by pin)
interrupt input
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• Active level selectable for each pin.
• Initial output level selectable for each pin.
• Synchronous operation (Refer to 20.2.3 Synchronous Operation .)
• Buffer operation (Refer to 20.2.2 Buffer Operation .)
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse Output
• A/D trigger generation
fk: Frequency of count source
m: Value set in the TRDGRAi register
n: Value set in the TRDGRji register
when the CSELi bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
stops at the compare match in the TRDGRAi register.
The PWM output pin holds level after output change by compare
match.
the TRDGRhi register.)
Either 1 pin or multiple pins of the TRDIOBi, TRDIOCi or TRDIODi
pin.
Forced Cutoff .)
n+1
m+1
m-n
Specification
(When “L” is selected as the active level)
Page 343 of 740
20. Timer RD