r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 393

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
20.6.4
Notes:
20.6.5
1. When the CSEL0 bit is set to 1, write 0 to the TSTART0 bit.
2. When the CSEL1 bit is set to 1, write 0 to the TSTART1 bit.
3. When the CSEL0 bit is set to 0 and the compare match signal (TRDIOA0) is generated, this bit is set to 0 (count
4. When the CSEL1 bit is set to 0 and the compare match signal (TRDIOA1) is generated, this bit is set to 0 (count
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0137h
Address 0138h
stops).
stops).
Set the TRDSTR register using the MOV instruction (do not use the bit handling instruction). Refer to 20.10.1
TRDSTR Register of Notes on Timer RD.
Symbol
Symbol
TSTART0 TRD0 count start flag
TSTART1 TRD1 count start flag
Symbol
Bit
Symbol
Bit
SYNC
CSEL0
CSEL1
BFC0
BFD0
BFC1
BFD1
Timer RD Start Register (TRDSTR) in Reset Synchronous PWM Mode
Timer RD Mode Register (TRDMR) in Reset Synchronous PWM Mode
—
—
—
—
—
—
—
BFD1
b7
b7
—
1
0
Timer RD synchronous bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
TRDGRC0 register function select bit 0: General register
TRDGRD0 register function select bit 0: General register
TRDGRC1 register function select bit 0: General register
TRDGRD1 register function select bit 0: General register
TRD0 count operation select bit
TRD1 count operation select bit
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
BFC1
b6
b6
—
1
0
Bit Name
Bit Name
BFD0
b5
—
b5
1
0
(3)
(4)
BFC0
b4
b4
—
1
0
Set this bit to 0 (registers TRD and TRD1 operate
independently) in reset synchronous PWM mode.
1: Buffer register of TRDGRA0 register
1: Buffer register of TRDGRB0 register
1: Buffer register of TRDGRA1 register
1: Buffer register of TRDGRB1 register
CSEL1
0: Count stops
1: Count starts
0: Count stops
1: Count starts
0: Count stops at the compare match with the
1: Count continues after the compare match with
0: Count stops at the compare match with the
1: Count continues after the compare match with
b3
b3
—
1
1
TRDGRA0 register
the TRDGRA0 register
TRDGRA1 register
the TRDGRA1 register
CSEL0 TSTART1 TSTART0
b2
b2
—
1
1
(1)
(2)
Function
Function
b1
b1
—
0
1
SYNC
b0
b0
0
0
Page 361 of 740
20. Timer RD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—