r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 404

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Table 20.13
i = 0 or 1, j = A, B, C, or D
Note:
Count sources
Count operations
PWM operations
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Selectable functions
1. After a count starts, the PWM period is fixed.
Item
Complementary PWM Mode Specifications
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
External signal input to the TRDCLK pin (valid edge selected by a program)
Set bits TCK2 to TCK0 in the TRDCR1 register to the same value (same count
source) as bits TCK2 to TCK0 in the TRDCR0 register.
Increment or decrement
Registers TRD0 and TRD1 are decremented with the compare match in registers
TRD0 and TRDGRA0 during increment operation. The TRD1 register value is
changed from 0000h to FFFFh during decrement operation, and registers TRD0 and
TRD1 are incremented.
PWM period: 1/fk × (m+2-p) × 2
Dead time: p
Active level width of normal-phase: 1/fk × (m-n-p+1) × 2
Active level width of counter-phase: 1/fk × (n+1-p) × 2
1 (count starts) is written to bits TSTART0 and TSTART1 in the TRDSTR register.
0 (count stops) is written to bits TSTART0 and TSTART1 when the CSEL0 bit in the
TRDSTR register is set to 1. (The PWM output pin outputs the initial output level
selected by bits OLS0 and OLS1 in the TRDFCR register.)
• Compare match (The content of the TRDi register matches content of the TRDGRji
• The TRD1 register underflows
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every 1/2 period of PWM
Programmable I/O port, pulse output forced cutoff signal input or INT0 interrupt input
The count value can be read by reading the TRDi register.
The value can be written to the TRDi register.
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse Output Forced
• The normal-phase and counter-phase active level and initial output level are
• Transfer timing from the buffer register selection
• A/D trigger generation
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output)
p: Value set in the TRD0 register
register.)
Cutoff. )
selected individually.
Counter-phase
Normal-phase
Value set in the TRDGRA1 register (PWM2 output)
Value set in the TRDGRB1 register (PWM3 output)
n+1-p
n+1
m+2-p
p
(1)
m-p-n+1
Specification
(When “L” is selected as the active level)
Page 372 of 740
20. Timer RD