r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 421

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Table 20.15
i = 0 or 1, j = A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0, TRDIOB0 pin
functions
TRDIOC0, TRDIOD0, TRDIOA1
to TRDIOD1 pin functions
INT0 pin function
Read from timer
Write to timer
Selectable functions
PWM3 Mode Specifications
Item
f1, f2, f4, f8, f32, fOCO40M, fOCO-F
The TRD0 register is incremented (the TRD1 is not used).
PWM period: 1/fk × (m+1)
Active level width of TRDIOA0 output: 1/fk × (m-n)
Active level width of TRDIOB0 output: 1/fk × (p-q)
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (The content of the TRDi register matches content
• The TRD0 register overflows
PWM output
Programmable I/O port
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• Pulse output forced cutoff signal input (Refer to 20.2.4 Pulse
• Buffer operation (Refer to 20.2.2 Buffer Operation. )
• Active level selectable for each pin
• A/D trigger generation
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRA1 register
p: Value set in the TRDGRB0 register
q: Value set in the TRDGRB1 register
register when the CSEL0 bit in the TRDSTR register is set to 1.
The PWM output pin holds output level before the count stops.
stops at compare match with the TRDGRA0 register.
The PWM output pin holds level after output change by compare
match.
of the TRDGRji register.)
Output Forced Cutoff. )
TRDIOA0 output
TRDIOB0 output
m+1
n+1
p+1
q+1
p-q
Specification
(When “H” is selected as the active level)
m-n
Page 389 of 740
20. Timer RD