r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 471

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 22.3
• Transmit Timing Example (Internal Clock Selected)
• Receive Timing Example (External Clock Selected)
SiTIC register
UiC1 register
UiC0 register
UiC1 register
Transfer clock
SiRIC register
UiC1 register
TXEPT bit in
The above applies when:
UiC1 register
UiC1 register
UiC1 register
The above applies when:
The following should be met when “H” is applied to the CLKi pin before receiving data:
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and
• UiIRS bit in UiC1 register = 0
fEXT: Frequency of external clock
i = 0 or 1
receive data input at the rising edge of the transfer clock)
(interrupt request generation when the transmit buffer is empty)
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and
• TE bit in UiC1 register = 1 (transmission enabled)
• RE bit in UiC1 register = 1 (reception enabled)
• Dummy data is written to UiTB register
RE bit in
TE bit in
receive data input at the rising edge of the transfer clock)
TE bit in
IR bit in
RI bit in
TI bit in
TI bit in
IR bit in
TXDi
CLKi
CLKi
RXDi
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in UiTB register.
Dummy data is set in UiTB register.
Data transfer from UARTi receive register
Data transfer from UiTB register to UARTi transmit register
Data transfer from UiTB register to UARTi transmit register
D0
D0
D1
D1
D2 D3
D2 D3
TCLK
1/fEXT
to UiRB register
D4
D4
TC
Receive data taken in
D5
D5
D6
D6
Set to 0 by an interrupt request acknowledgement or by a program.
D7
D7
D0 D1
D0 D1
Set to 0 when an interrupt request is acknowledged or by a program.
D2 D3
D2
Data read from UiRB register
D3
D4
D5
D4 D5
D6
TC = TCLK = 2(n+1)/fi
D7
fi: Frequency of UiBRG count source (f1, f8, f32, fC)
n: Setting value in UiBRG register
Pulsing stops because TE bit is set to 0.
22. Serial Interface (UARTi (i = 0 or 1))
D0 D1
D2
D3
D4
D5
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D6
D7