r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 497

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 23.3
(1) Transmit Timing Example (Internal Clock Selected)
(2) Receive Timing Example (External Clock Selected)
The above applies when:
The above applies when:
fEXT: Frequency of external clock
• U2IRS bit in U2C1 register = 0 (interrupt request generation when the U2TB register is empty)
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
• CKPOL bit in U2C0 register = 0 (transmit data output at the falling edge and
• CKDIR bit in U2MR register = 0 (internal clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 0 (CTS function selected)
S2RIC register
• CKDIR bit in U2MR register = 1 (external clock)
• CRD bit in U2C0 register = 0 (CTS/RTS function enabled), CRS bit = 1 (RTS function selected)
U2RB register
U2C1 register
U2C1 register
U2C1 register
U2C1 register
receive data input at the rising edge of the transfer clock)
receive data input at the rising edge of the transfer clock)
OER flag in
S2TIC register
Transfer clock
U2C1 register
U2C1 register
TXEPT flag in
U2C0 register
RE bit in
TE bit in
RI bit in
IR bit in
TI bit in
RXD2
RTS2
CLK2
TE bit in
IR bit in
TI bit in
CTS2
CLK2
TXD2
Data transfer from UART2 receive
register to U2RB register
Transmit and Receive Timing in Clock Synchronous Serial I/O Mode
Data is set in U2TB register.
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Dummy data is set in U2TB register.
Data transfer from U2TB register to UART2 transmit register
Set to 0 when an interrupt request is acknowledged or by a program.
TCLK
1/fEXT
Received data taken in
TC
Data transfer from U2TB register to UART2 transmit register
Data read from U2RB register
Pulsing stops because “H” is applied
to CTS2.
D0 D1 D2 D3 D4 D5
Set to 0 when an interrupt request is acknowledged or by a program.
“L” is applied when U2RB register is read.
D0 D1 D2 D3 D4 D5 D6 D7
D6
D7
Make sure the following conditions are met
when the CLK2 pin input before receiving data is high:
• TE bit in U2C0 register = 1 (transmission enabled)
• RE bit in U2C1 register = 1 (reception enabled)
• Dummy data is written to U2TB register
D0 D1 D2 D3 D4 D5
TC = TCLK = 2(n+1)/fj
Pulsing stops because TE bit is set to 0.
fj: Frequency of U2BRG count source
n: Setting value in U2BRG register
D0 D1 D2 D3 D4 D5 D6 D7
(f1, f8, f32, fC)
23. Serial Interface (UART2)
D6
Page 465 of 740