r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 505

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 23.8
23.4.1
Table 23.8
Note:
Bit Rate
115200
14400
19200
28800
38400
57600
(bps)
1200
2400
4800
9600
Receive Timing Example When Transfer Data is 8 Bits Long (Parity Disabled, One Stop Bit)
1. For the high-speed on-chip oscillator, the correction value in the FRA4 register should be written into the FRA1
In UART mode, the bit rate is the frequency divided by the U2BRG register divided by 16. Table 23.8 lists the
Bit Rate Setting Example in UART Mode (Internal Clock Selected).
S2RIC register
register and the correction value in the FRA5 register should be written into the FRA3 register.
This applies when the high-speed on-chip oscillator is selected as the system clock and bits FRA22 to FRA20
in the FRA2 register are set to 000b (divide-by-2 mode). For the precision of the high-speed on-chip oscillator,
refer to 34. Electrical Characteristics .
U2C1 register
U2C1 register
Transfer clock
count source
U2BRG
Source
Count
RE bit in
Bit Rate
U2BRG
RI bit in
IR bit in
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
RXD2
RTS2
Receive Timing in UART Mode
Bit Rate Setting Example in UART Mode (Internal Clock Selected)
The above applies when:
• PRYE bit in U2MR register = 0 (parity disabled)
• STPS bit in U2MR register = 0 (one stop bit)
• CRD bit in U2C0 register = 0 (CTS2/RTS2 function enabled), CRS bit = 1 (RTS2 function selected)
129 (81h)
129 (81h)
42 (2Ah)
10 (0Ah)
64 (40h)
32 (20h)
86 (56h)
64 (40h)
32 (20h)
21 (15h)
U2BRG
Setting
Value
System Clock = 20 MHz
Reception starts when a transfer clock
is generated at the falling edge
of the start bit.
Actual Time
Start bit
113636.36
29069.77
56818.18
14367.82
19230.77
37878.79
(bps)
1201.92
2403.85
4734.85
9615.38
“L” is determined.
Setting
Error
(%)
-1.36 29 (1Dh)
-0.22 79 (4Fh)
-1.36 29 (1Dh)
-1.36 19 (13h)
-1.36
0.16 119 (77h)
0.16 59 (3Bh)
0.16 119 (77h)
0.16 59 (3Bh)
0.94 39 (27h)
System Clock = 18.432 MHz
U2BRG
9 (09h)
Setting
D0
Value
Set to 0 when an interrupt request is acknowledged or by a program.
Receive data taken in
Data transfer from UART2 receive register
to U2RB register
Actual Time
115200.00
14400.00
19200.00
28800.00
38400.00
57600.00
(bps)
1200.00
2400.00
4800.00
9600.00
D1
D7
Setting
Error
(%)
0.00 51 (33h)
0.00 25 (19h)
0.00 12 (0Ch)
0.00 51 (33h)
0.00 34 (22h) 14285.71
0.00 25 (19h) 19230.77
0.00 16 (10h)
0.00 12 (0Ch) 38461.54
0.00
0.00
(1)
23. Serial Interface (UART2)
U2BRG
Setting
8 (08h)
Value
Stop bit
System Clock = 8 MHz
−
55555.56
29411.76
1201.92
2403.85
4807.69
9615.38
Actual
(bps)
Time
Page 473 of 740
−
Setting
Error
(%)
-0.79
-3.55
0.16
0.16
0.16
0.16
0.16
2.12
0.16
−