r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 508

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 23.12
23.4.6
23.4.7
input signal
Sampling
The CTS function is used to start transmit operation when “L” is applied to the CTS2/RTS2 pin. Transmit
operation begins when the CTS2/RTS2 pin is held low. If the “L” signal is switched to “H” during transmit
operation, the operation stops after the ongoing transmit/receive operation is completed.
When the RTS function is used, the CTS2/RTS2 pin outputs “L” when the MCU is ready for a receive
operation.
• The CRD bit in the U2C0 register = 1 (CTS/RTS function disabled)
• The CRD bit = 0, CRS bit = 0 (CTS function selected)
• The CRD bit = 0, CRS bit = 1 (RTS function selected)
When the DF2EN bit in the URXDF register is set to 1 (RXD2 digital filer enabled), the RXD2 input signal is
loaded internally via the digital filter circuit for noise reduction. The noise canceller consists of three cascaded
latch circuits and a match detection circuit. The RXD2 input signal is sampled on the internal basic clock with a
frequency 16 times the bit rate. It is recognized as a signal and the level is passed forward to the next circuit
when three latch outputs match. When the outputs do not match, the previous value is retained.
In other words, when the level is changed within three clocks, the change is recognized as not a signal but noise.
Figure 23.12 shows a Block Diagram of RXD2 Digital Filter Circuit.
RXD2
clock
The CTS2/RTS2 pin operates as the programmable I/O function.
The CTS2/RTS2 pin operates as the CTS function.
The CTS2/RTS2 pin operates as the RTS function.
CTS/RTS Function
RXD2 Digital Filter Select Function
Note:
Internal basic clock
Block Diagram of RXD2 Digital Filter Circuit
1. When the CKDIR bit in the U2MR register is 0 (internal clock), the internal basic clock is set to fj/(n+1)
Sampling clock
D
period
(fj = f1, f8, f32, fC; n = setting value in the U2BRG register).
When the CKDIR bit in the U2MR register is 1 (external clock), the internal basic clock is set to fEXT/(n+1)
(fEXT is input from the CLK2 pin. n = setting value in the U2BRG register).
Latch
C
(1)
Q
D
Latch
C
Q
D
Latch
C
Q
detection
Match
circuit
(DF2EN bit)
23. Serial Interface (UART2)
URXDF
register
Page 476 of 740
Internal RXD2
input signal