r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 520

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 23.18
Reception
Transmission
RXD2
DF2EN = 1
DF2EN = 0
Digital
filter
[Multiprocessor mode reception when MP = 1 (multiprocessor communication enabled)]
[Multiprocessor mode transmission when MP = 1 (multiprocessor communication enabled)]
[Multiprocessor mode transmission/reception]
SP
Block Diagram of Multiprocessor Communication Function
(1) Clock asynchronous (7 bits): Received D7 is transferred to b8 in the U2RB register.
(2) Clock asynchronous (8 bits): Received D8 is transferred to b8 in the U2RB register.
(3) Clock asynchronous (7 bits): b8 in the U2TB register is transferred externally as transfer data D7.
(4) Clock asynchronous (8 bits): b8 in the U2TB register is transferred externally as transfer data D8.
(5) PAR is disabled.
SP
SP
2SP
1SP
2SP
1SP
SP
PAR
PAR
0
(5)
(5)
PAR
enabled
PRYE = 1
PAR
disabled
PRYE = 0
PRYE = 0
PAR
disabled
PAR
enabled
PRYE = 1
0
0
0
Clock
synchronous
type
Clock
synchronous
type
0
UART
UART
0
0
(4)
UART
(9 bits)
UART
(9 bits)
0
Clock
synchronous type
UART (7 bits)
UART (8 bits)
(2)
UART (7 bits)
UART (8 bits)
Clock
synchronous type
MPTB
MPRB
(3)
(1)
Data bus high-order bits
Data bus low-order bits
Clock
synchronous
type
UART (8 bits)
UART (9 bits)
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
UART
(7 bits)
UART
(7 bits)
D7
D7
D6
D6
MSB/LSB conversion circuit
MSB/LSB conversion circuit
D5
D5
23. Serial Interface (UART2)
D4
D4
UART2 receive register
UART2 transmit register
SP: Stop bit
PAR: Parity bit
PRYE: Bit in U2MR
DF2EN: Bit in URXDF
MP: Bit in U2SMR5
D3
D3
D2
D2
Page 488 of 740
D1
D1
D0
D0
register
register
register
U2RB
register
U2TB
register
TXD2