r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 535

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
25.2.8
Note:
1. Refer to 25.3.1.1 Association between Transfer Clock Polarity, Phase, and Data for the settings of the CPHS
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ah
and CPOS bits.
When the SSUMS bit in the SSMR2 register is set to 0 (clock synchronous communication mode), set the CPHS
bit to 0 and the CPOS bit to 0.
Symbol
Symbol
CPOS
Bit
CPHS
MLS
BC0
BC1
BC2
BC3
SS Mode Register (SSMR)
—
MLS
b7
0
Bits counter 3 to 0
Nothing is assigned. If necessary, set to 0. When read, the content is 1.
SSCK clock phase select bit
SSCK clock polarity select bit
MSB first/LSB first select bit
CPOS
b6
0
Bit Name
CPHS
b5
0
(1)
(1)
b4
—
1
b3 b2 b1 b0
0: Change data at odd edge
1: Change data at even edge
0: “H” when clock stops
1: “L” when clock stops
0: Transfers data MSB first
1: Transfers data LSB first
0 0 0 0: 16 bits left
0 0 0 1: 1 bit left
0 0 1 0: 2 bits left
0 0 1 1: 3 bits left
0 1 0 0: 4 bits left
0 1 0 1: 5 bits left
0 1 1 0: 6 bits left
0 1 1 1: 7 bits left
1 0 0 0: 8 bits left
1 0 0 1: 9 bits left
1 0 1 0: 10 bits left
1 0 1 1: 11 bits left
1 1 0 0: 12 bits left
1 1 0 1: 13 bits left
1 1 1 0: 14 bits left
1 1 1 1: 15 bits left
BC3
b3
(Download data at even edge)
(Download data at odd edge)
0
25. Synchronous Serial Communication Unit (SSU)
BC2
b2
0
Function
BC1
b1
0
BC0
b0
0
Page 503 of 740
R/W
R/W
R/W
R/W
—
R
R
R
R