r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 537

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
25.2.10 SS Status Register (SSSR)
Notes:
1. Writing 1 to CE, ORER, RDRF, TEND, or TDRE bits is invalid. To set any of these bits to 0, first read 1 then write
2. When the serial communication is started while the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus
3. Indicates when overrun errors occur and receive completes by error reception. If the next serial data receive
4. The RDRF bit is set to 0 when reading out the data from the SSRDR register.
5. Bits TEND and TDRE are set to 0 when writing data to the SSTDR register.
6. The TDRE bit is set to 1 when the TE bit in the SSER register is set to 1 (transmit enabled).
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 019Ch
0.
communication mode) and the MSS bit in the SSCRH register is set to 1 (operates as master device), the CE bit
is set to 1 if “L” is applied to the SCS pin input. Refer to 25.5.4 SCS Pin Control and Arbitration for more
information.
When the SSUMS bit in the SSMR2 register is set to 1 (four-wire bus communication mode), the MSS bit in the
SSCRH register is set to 0 (operates as slave device) and the SCS pin input changes the level from “L” to “H”
during transfer, the CE bit is set to 1.
operation is completed while the RDRF bit is set to 1 (data in the SSRDR register), the ORER bit is set to 1.
After the ORER bit is set to 1 (overrun error), receive operation is disabled while the bit remains 1.
When reading these bits immediately after writing to the SSTDR register, insert three or more NOP instructions
between the instructions used for writing and reading.
If the SSSR register is accessed continuously, insert one or more NOP instructions between the instructions
used for access.
Symbol
Symbol
ORER
Bit
RDRF
TEND
TDRE
CE
—
—
—
TDRE
b7
0
Conflict error flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Overrun error flag
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Receive data register full flag
Transmit end flag
Transmit data empty flag
TEND
b6
0
Bit Name
(1)
RDRF
(1, 5)
(1)
b5
0
(1, 5, 6)
(1, 4)
b4
—
0
0: No conflict errors generated
1: Conflict errors generated
0: No overrun errors generated
1: Overrun errors generated
0: No data in SSRDR register
1: Data in SSRDR register
0: The TDRE bit is set to 0 when transmitting the last
1: The TDRE bit is set to 1 when transmitting the last
0: Data is not transferred from registers SSTDR to
1: Data is transferred from registers SSTDR to
bit of transmit data
bit of transmit data
SSTRSR
SSTRSR
b3
—
0
25. Synchronous Serial Communication Unit (SSU)
ORER
b2
0
Function
b1
—
0
(2)
(3)
CE
b0
0
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R/W
R/W
R/W
R/W
R/W
R/W
—
—