r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 542

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
25.3.3
Table 25.3
CEIE, RIE, TEIE and TIE: Bits in SSER register
ORER, RDRF, TEND and TDRE: Bits in SSSR register
Transmit data empty
Transmit end
Receive data full
Overrun error
Conflict error
If the generation conditions in Table 25.3 are met, a synchronous serial communication unit interrupt request is
generated. Set each interrupt source to 0 by a synchronous serial communication unit interrupt routine.
However, the TDRE and TEND bits are automatically set to 0 by writing transmit data to the SSTDR register and
the RDRF bit is automatically set to 0 by reading the SSRDR register. In particular, the TDRE bit is set to 1 (data
transmitted from registers SSTDR to SSTRSR) at the same time transmit data is written to the SSTDR register.
Setting the TDRE bit to 0 (data not transmitted from registers SSTDR to SSTRSR) can cause an additional byte of
data to be transmitted.
Synchronous serial communication unit has five interrupt requests: transmit data empty, transmit end, receive
data full, overrun error, and conflict error. Since these interrupt requests are assigned to the synchronous serial
communication unit interrupt vector table, determining interrupt sources by flags is required.
Table 25.3 shows the Synchronous Serial Communication Unit Interrupt Requests.
Interrupt Request
Interrupt Requests
Synchronous Serial Communication Unit Interrupt Requests
TXI
TEI
RXI
OEI
CEI
Abbreviation
25. Synchronous Serial Communication Unit (SSU)
TIE = 1, TDRE = 1
TEIE = 1, TEND = 1
RIE = 1, RDRF = 1
RIE = 1, ORER = 1
CEIE = 1, CE = 1
Generation Condition
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