r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 548

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 25.8
(1)
(2)
(3)
(4)
(5)
(6)
(7)
SSCRH register
SSCRH register
SSER register
Mode)
Sample Flowchart of Data Reception (MSS = 1) (Clock Synchronous Communication
Read receive data in SSRDR register
Read receive data in SSRDR register
Read ORER bit in SSSR register
Read ORER bit in SSSR register
Read RDRF bit in SSSR register
Dummy read of SSRDR register
Read RDRF in SSSR register
No
No
ORER = 1 ?
ORER = 1 ?
Initialization
RDRF = 1 ?
RDRF = 1 ?
received?
Last data
Start
End
RSSTP bit ← 1
RSSTP bit ← 0
RE bit ← 0
No
No
Yes
No
Yes
Yes
Yes
Yes
processing
Overrun
error
25. Synchronous Serial Communication Unit (SSU)
(3) If a receive error occurs, perform error
(6) processing after reading the ORER bit. Then set
(1) After setting each register in the synchronous serial
(2) Determine whether it is the last 1 byte of data to be
(4) Confirm that the RDRF bit is set to 1. If the RDRF
(5) Before the last 1 byte of data is received, set the
(7) Confirm that the RDRF bit is set to 1. When the
the ORER bit to 0. Transmission/reception cannot
be restarted while the ORER bit is set to 1.
communication unit register, a dummy read of the
SSRDR register is performed and the receive
operation is started.
received. If so, set to stop after the data is received.
bit is set to 1, read the receive data in the SSRDR
register. When the SSRDR register is read, the
RDRF bit is automatically set to 0.
RSSTP bit to 1 and stop after the data is
received.
receive operation is completed, set the RSSTP bit to
0 and the RE bit to 0 before reading the last 1 byte
of data. If the SSRDR register is read before setting
the RE bit to 0, the receive operation is restarted
again.
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