r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 549

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r5f21346mnfp

Manufacturer Part Number
r5f21346mnfp
Description
Single-chip Mcus Incorporates The R8c Cpu Core
Manufacturer
Renesas Electronics Corporation.
Datasheet

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Part Number:
r5f21346mnfp#V0
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R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
25.4.3.1
Data transmission/reception is an operation combining data transmission and reception which were described
earlier. Transmission/reception is started by writing data to the SSTDR register.
When the last transfer clock (The data transfer length can be set from 8 to 16 bits using the SSBR register) rises
or the ORER bit is set to 1 (overrun error) while the TDRE bit is set to 1 (data is transferred from registers
SSTDR to SSTRSR), the transmit/receive operation is stopped.
When switching from transmit mode (TE = 1) or receive mode (RE = 1) to transmit/receive mode (TE = RE =
1), set the TE bit to 0 and RE bit to 0 before switching. After confirming that the TEND bit is set to 0 (the
TDRE bit is set to 0 when the last bit of the transmit data is transmitted), the RDRF bit is set to 0 (no data in the
SSRDR register), and the ORER bit is set to 0 (no overrun error), set bits TE and RE to 1.
Figure 25.9 shows a Sample Flowchart of Data Transmission/Reception (Clock Synchronous Communication
Mode).
When exiting transmit/receive mode after this mode is used (TE = RE = 1), a clock may be output if
transmit/receive mode is exited after reading the SSRDR register. To avoid any clock outputs, perform either of
the following:
- First set the RE bit to 0, and then set the TE bit to 0.
- Set bits TE and RE to 0 at the same time.
When subsequently switching to receive mode (TE = 0 and RE = 1), first set the SRES bit to 1, and set this bit
to 0 to reset the SSU control unit and the SSTRSR register. Then, set the RE bit to 1.
Data Transmission/Reception
25. Synchronous Serial Communication Unit (SSU)
Page 517 of 740

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