r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 576

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
26.4.2
In master transmit mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figures 26.5 and 26.6 show the Operating Timing in Master Transmit Mode (I
The transmit procedure and operation in master transmit mode are as follows.
(1) Set the STOP bit in the ICSR register to 0 for initialization, and set the ICE bit in the ICCR1 register to 1
(2) After confirming that the bus is released by reading the BBSY bit in the ICCR2 register, set bits TRS and
(3) After confirming that the TDRE bit in the ICSR register is set to 1 (data is transferred from registers ICDRT
(4) When 1 byte of data transmission is completed while the TDRE bit is set to 1, the TEND bit in the ICSR
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set to 1.
(6) When the number of bytes to be transmitted is written to the ICDRT register, wait until the TEND bit is set
(7) When the STOP bit in the ICSR register is set to 1, return to slave receive mode.
(transfer operation enabled). Then, set bits WAIT and MLS in the ICMR register and bits CKS0 to CKS3 in
the ICCR1 register (initial setting).
MST in the ICCR1 register to master transmit mode. Then, write 1 to the BBSY bit and 0 to the SCP bit
with the MOV instruction (start condition generated). This will generate a start condition.
to ICDRS), write transmit data to the ICDRT register (data in which a slave address and R/W are indicated
in the 1st byte). At this time, the TDRE bit is automatically set to 0. When data is transferred from registers
ICDRT to ICDRS, the TDRE bit is set to 1 again.
register is set to 1 at the rising edge of the 9th clock cycle of the transmit clock. After confirming that the
slave device is selected by reading the ACKBR bit in the ICIER register, write the 2nd byte of data to the
ICDRT register. Since the slave device is not acknowledged when the ACKBR bit is set to 1, generate a
stop condition. Stop condition generation is enabled by writing 0 to the BBSY bit and 0 to the SCP bit with
the MOV instruction. The SCL signal is fixed “L” until data is ready or a stop condition is generated.
to 1 while the TDRE bit is set to 1. Or wait for NACK (NACKF bit in ICSR register = 1) from the receive
device while the ACKE bit in the ICIER register is set to 1 (when the receive acknowledge bit is set to 1,
transfer is halted). Then, generate a stop condition before setting the TEND bit or the NACKF bit to 0.
Master Transmit Operation
2
C bus Interface Mode).
26. I
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2
C bus Interface