r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 578

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
26.4.3
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figures 26.7 and 26.8 show the Operating Timing in Master Receive Mode (I
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, set the TRS bit in the ICCR1 register to 0 to switch
(2) Dummy reading the ICDRR register starts receive operation. The receive clock is output in synchronization
(3) When 1-frame of data reception is completed, the RDRF bit in the ICSR register is set to 1 at the rising
(4) Continuous receive operation is enabled by reading the ICDRR register every time the RDRF bit is set to 1.
(5) If the next frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1 (next receive
(6) When the RDRF bit is set to 1 at the rising edge of the 9th clock cycle of the receive clock, generate a stop
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register and set the RCVD bit to 0 (next
(8) Return to slave receive mode.
from master transmit mode to master receive mode. Then set the TDRE bit in the ICSR register to 0.
with the internal clock and data is received. The master device outputs the level set by the ACKBT bit in
the ICIER register to the SDA pin at the rising edge of the 9th clock cycle of the receive clock.
edge of the 9th clock cycle of the receive clock. At this time, if the ICDRR register is read, the received
data can be read and the RDRF bit is set to 0 simultaneously.
If reading the ICDRR register is delayed by another process and the 8th clock cycle falls while the RDRF
bit is set to 1, the SCL signal is fixed “L” until the ICDRR register is read.
operation disabled) before reading the ICDRR register, stop condition generation is enabled after the next
receive operation.
condition. When a stop condition generation or a start condition regeneration overlaps with the falling edge
of the ninth clock cycle of SCL, an additional cycle is output after the ninth clock cycle. Refer to 26.9
Notes on I
receive operation continues).
Master Receive Operation
2
C bus Interface.
2
C bus Interface Mode).
26. I
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2
C bus Interface