r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 600

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
27.4
Figure 27.2
27.4.1
TRAIC register
LINST register
Figure 27.2 shows an Operating Example during Header Field Transmission in master mode. Figures 27.3 and
27.4 show Examples of Header Field Transmission Flowchart.
During header field transmission, the hardware LIN operates as follows:
(1) When 1 is written to the TSTART bit in the TRACR register for timer RA, a “L” level is output from the
(2) When timer RA underflows, the TXD0 pin output is inverted and the SBDCT flag in the LINST register is
(3) The hardware LIN transmits “55h” via UART0.
(4) After the hardware LIN completes transmitting “55h”, it transmits an ID field via UART0.
(5) After the hardware LIN completes transmitting the ID field, it performs communication for a response
SBDCT flag in
Function Description
TXD0 pin for the period set in registers TRAPRE and TRA for timer RA.
set to 1. If the SBIE bit in the LINCR register is set to 1, a timer RA interrupt is generated.
field.
TXD0 pin
IR bit in
Master Mode
Operating Example during Header Field Transmission
The above applies when:
LINE = 1, MST = 1, SBIE = 1
(1)
Synch Break
(2)
(3)
Set to 0 when an interrupt request is acknowledged
or by a program.
1 is written to B1CLR bit in LINST register.
Synch Field
(4)
IDENTIFIER
27. Hardware LIN
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(5)