r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 665

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
32.4
Table 32.3
Operating mode
Rewrite control program
allocatable area
Rewrite control program
executable areas
Rewritable area
Software command
restrictions
Mode after programming or
block erasure or after
entering erase-suspend
CPU and DTC state during
programming and
block erasure
Flash memory
status detection
Conditions for entering
erase-suspend
CPU clock
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the MCU is mounted on a board without using a
ROM programmer. Execute the software command only to blocks in the user ROM area.
The flash module has an erase-suspend function which halts the erase operation temporarily during an erase
operation in CPU rewrite mode. During erase-suspend, the flash memory can be read or programmed.
Erase-write 0 mode (EW0 mode) and erase-write 1 mode (EW1 mode) are available in CPU rewrite mode.
Table 32.3 lists the Differences between EW0 Mode and EW1 Mode.
CPU Rewrite Mode
Item
Differences between EW0 Mode and EW1 Mode
Single-chip mode
User ROM
RAM (The rewrite control program must
be transferred before being executed.)
However, the program can be executed
in the program ROM area when rewriting
the data flash area.
User ROM
—
Read array mode
The CPU operates.
Read bits FST7, FST5, and FST4 in
the FST register by a program.
• Set bits FMR20 and FMR21 in the
• Set bits FMR20 and FMR22 in the
Max. 20 MHz
FMR2 register to 1 by a program.
FMR2 register to 1 and the enabled
maskable interrupt is generated.
EW0 Mode
Single-chip mode
User ROM
User ROM or RAM
User ROM
Program and block erase commands
Read array mode
• The CPU or DTC operates while the data
• The CPU or DTC is put in a hold state
Read bits FST7, FST5, and FST4 in
the FST register by a program.
• Set bits FMR20 and FMR21 in the FMR2
• Set bits FMR20 and FMR22 in the FMR2
Max. 20 MHz
flash area is being programmed or block
erased.
while the program ROM area is being
programmed or block erased. (I/O ports
retain the state before the command
execution).
register to 1 by a program (while rewriting
the data flash area).
register to 1 and the enabled maskable
interrupt is generated.
However, blocks which contain the
rewrite control program are excluded.
Cannot be executed to any block which
contains the rewrite control program.
EW1 Mode
32. Flash Memory
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