r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 697

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
32.7
32.7.1
Table 32.9
FMR21, FMR22: Bits in FMR2 register
EW0
EW1
Mode
32.7.1.1
32.7.1.2
The following instructions cannot be used while the program ROM area is being rewritten in EW0 mode
because they reference data in the flash memory: UND, INTO, and BRK.
Tables 32.9 to 32.11 show CPU Rewrite Mode Interrupts (1), (2) and (3), respectively.
Notes on Flash Memory
Data
flash
Program
ROM
Data
flash
Program
ROM
Erase/
Target
Write
CPU Rewrite Mode
Prohibited Instructions
Interrupts
CPU Rewrite Mode Interrupts (1)
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled)
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
During
auto-programming
During auto-erasure
(suspend enabled)
During auto-erasure
(suspend disabled
or FMR22 = 0)
During
auto-programming
Status
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1 (erase-suspend request enabled by interrupt request),
the FMR21 bit is automatically set to 1 (erase-suspend request). The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0 (erase-suspend request
disabled by interrupt request), set the FMR21 bit to 1 during interrupt handling. The flash
memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read or written. Auto-erasure can be restarted by setting the
FMR21 bit to 0 (erase restart).
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
Usable by allocating a vector in RAM.
When an interrupt request is acknowledged, interrupt handling is executed.
If the FMR22 bit is set to 1, the FMR21 bit is automatically set to 1. The flash memory
suspends auto-erasure after td(SR-SUS).
If erase-suspend is required while the FMR22 bit is set to 0, set the FMR21 bit to 1 during
interrupt handling. The flash memory suspends auto-erasure after td(SR-SUS).
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read or written. Auto-erasure can be restarted by setting the
FMR21 bit to 0.
Interrupt handling is executed while auto-erasure or auto-programming is being
performed.
Auto-erasure suspends after td(SR-SUS) and interrupt handling is executed. Auto-
erasure can be restarted by setting the FMR21 bit to 0 after interrupt handling completes.
While auto-erasure is being suspended, any block other than the block during auto-
erasure execution can be read or written.
Auto-erasure and auto-programming have priority and interrupt requests are put on
standby. Interrupt handling is executed after auto-erase and auto-program complete.
Maskable Interrupt
32. Flash Memory
Page 665 of 740