r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 734

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
35. Usage Notes
35.1
35.1.1
35.1.2
To enter stop mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and then the
CM10 bit in the CM1 register to 1 (stop mode). An instruction queue pre-reads 4 bytes from the instruction
which sets the CM10 bit to 1 (stop mode) and the program stops.
Insert at least four NOP instructions following the JMP.B instruction after the instruction which sets the CM10
bit to 1.
• Program example to enter stop mode
When entering wait mode, set the FMR01 bit in the FMR0 register to 0 (CPU rewrite mode disabled) and the
FMR27 bit to 0 (low-current-consumption read mode disabled) before entering the mode. Do not enter wait
mode while the FMR01 bit is 1 (CPU rewrite mode enabled) or the FMR27 bit is 1 (low-current-consumption
read mode enabled).
To enter wait mode by setting the CM30 bit to 1, set the I flag to 0 (maskable interrupt disabled).
To enter wait mode using the WAIT instruction, set the I flag to 1 (maskable interrupt enabled). An instruction
queue pre-reads 4 bytes from the instruction to set the CM30 bit to 1 (MCU enters wait mode) or the WAIT
instruction, and then the program stops. Insert at least four NOP instructions after the instruction to set the
CM30 bit to 1 (MCU enters wait mode) or the WAIT instruction.
• Program example to execute the WAIT instruction
• Program example to execute the instruction to set the CM30 bit to 1
Notes on Clock Generation Circuit
Stop Mode
Wait Mode
LABEL_001:
BCLR
BCLR
BSET
FSET
BSET
JMP.B
NOP
NOP
NOP
NOP
BCLR
BCLR
FSET
WAIT
NOP
NOP
NOP
NOP
BCLR
BCLR
BSET
FCLR
BSET
NOP
NOP
NOP
NOP
BCLR
FSET
1,FMR0
7, FMR2
0,PRCR
I
0,CM1
LABEL_001
1,FMR0
7, FMR2
I
1, FMR0
7, FMR2
0, PRCR
I
0, CM3
0, PRCR
I
; CPU rewrite mode disabled
; Low-current-consumption read mode
; Writing to CM1 register enabled
; Interrupt enabled
; Stop mode
; CPU rewrite mode disabled
; Low-current-consumption read mode
; Interrupt enabled
; Wait mode
; CPU rewrite mode disabled
; Low-current-consumption read mode
; Writing to CM3 register enabled
; Interrupt disabled
; Wait mode
; Writing to CM3 register disabled
; Interrupt enabled
disabled
disabled
disabled
35. Usage Notes
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