r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 746

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
35.9
35.9.1
Table 35.1
35.9.2
35.9.3
35.9.4
When the CSELi bit is set to 1, set the
TSTARTi bit to 0 and the count stops.
When the CSELi bit is set to 0, the
count stops at compare match of
registers TRDi and TRDGRAi.
•
•
•
•
•
When writing the value to the TRDSRi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
To set bits TCK2 to TCK0 in the TRDCRi register to 111b (fOCO-F), set fOCO-F to the clock frequency higher
than the CPU clock frequency.
Set the TRDSTR register using the MOV instruction.
When the CSELi (i = 0 to 1) bit is set to 0 (the count stops at compare match of registers TRDi and
TRDGRAi), the count does not stop and the TSTARTi bit remains unchanged even if 0 (count stops) is
written to the TSTARTi bit.
Therefore, set the TSTARTi bit to 0 to change other bits without changing the TSTARTi bit when the CSELi
bit is se to 0.
To stop counting by a program, set the TSTARTi bit after setting the CSELi bit to 1. Although the CSELi bit
is set to 1 and the TSTARTi bit is set to 0 at the same time (with 1 instruction), the count cannot be stopped.
Table 35.1 lists the TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops to use the TRDIOji (j =
A, B, C, or D) pin with the timer RD output.
When writing the value to the TRDi register by a program while the TSTARTi bit in the TRDSTR register is
set to 1 (count starts), avoid overlapping with the timing for setting the TRDi register to 0000h, and then write.
If the timing for setting the TRDi register to 0000h overlaps with the timing for writing the value to the TRDi
register, the value is not written and the TRDi register is set to 0000h.
These precautions are applicable when selecting the following by bits CCLR2 to CCLR0 in the TRDCRi
register.
- 001b (Clear the TRDi register by input capture/compare match in the TRDGRAi register.)
- 010b (Clear the TRDi register by input capture/compare match in the TRDGRBi register.)
- 011b (Synchronous clear)
- 101b (Clear the TRDi register by input capture/compare match in the TRDGRCi register.)
- 110b (Clear the TRDi register by input capture/compare match in the TRDGRDi register.)
When writing the value to the TRDi register and continuously reading the same register, the value before
writing may be read. In this case, execute the JMP.B instruction between the writing and reading.
Notes on Timer RD
TRDSTR Register
TRDi Register (i = 0 or 1)
TRDSRi Register (i = 0 or 1)
TRDCRi Register (i = 0 or 1)
Count Stop
Program example
Program example
TRDIOji (j = A, B, C, or D) Pin Output Level when Count Stops
L1:
L1:
The pin holds the output level immediately before the count stops. (The pin
outputs the initial output level selected by bits OLS0 and OLS1 in the
TRDFCR register in complementary and reset synchronous PWM modes.)
The pin holds the output level after the output changes by compare match.
(The pin outputs the initial output level selected by bits OLS0 and OLS1 in the
TRDFCR register in complementary and reset synchronous PWM modes.)
MOV.W
JMP.B
MOV.W
MOV.B
JMP.B
MOV.B
TRDIOji Pin Output when Count Stops
#XXXXh, TRD0
L1
TRD0,DATA
#XXh, TRDSR0
L1
TRDSR0,DATA
;Writing
;JMP.B
;Reading
;Writing
;JMP.B
;Reading
35. Usage Notes
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