r5f21346mnfp Renesas Electronics Corporation., r5f21346mnfp Datasheet - Page 748

• Manufacturer Part Number: r5f21346mnfp
• Description: Single-chip Mcus Incorporates The R8c Cpu Core
• Manufacturer: Renesas Electronics Corporation.

R8C/34M Group
R01UH0131EJ0100 Rev.1.00
Jun 21, 2011
Figure 35.2
35.9.8
TRDGRB0 register
TRDGRA1 register
TRDGRB1 register
TRDSR0 register
Count value in TRD0
Setting value in
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•
Switching procedure: When setting to complementary PWM mode (including re-set), or changing the transfer
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 in the TRDFCR register to 00b (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 to CMD0 to 10b or 11b (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Switching procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD to 00b (timer mode, PWM mode, and PWM3 mode).
•
•
register
When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
Change bits CMD1 to CMD0 in the TRDFCR register in the following procedure.
Do not write to TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and
TRDGRD1 to registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits BFD0, BFC1, and
BFD1 to 0 (general register). After this, bits BFD0, BFC1, and BFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
If the value in the TRDGRA0 register is assumed to be m, the TRD0 register counts m-1, m, m+1, m, m-1, in
that order, when changing from increment to decrement operation.
When changing from m to m+1, the IMFA bit is set to 1. Also, bits CMD1 to CMD0 in the TRDFCR register
are set to 11b (complementary PWM mode, buffer data transferred at compare match between registers TRD0
and TRDGRA0), the content in the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is transferred
to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During m+1, m, and m-1 operation, the IMFA bit remains unchanged and data are not transferred to registers
such as the TRDGRA0 register.
TRDGRA0
IMFA bit in
Complementary PWM Mode
register
m
Complementary PWM Mode
Operation at Compare Match between Registers TRD0 and TRDGRA0 in
Set to 0 by a program
Transferred from
buffer register
timing from the buffer register to the general register in complementary PWM mode.
m+1
No change
Not transferred from buffer register
When bits CMD1 to CMD0 in the
TRDFCR register are set to 11b
(transfer from the buffer register to the
general register at compare match of
between registers TRD0 and
TRDGRA0).
35. Usage Notes
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