mb91307r Fujitsu Microelectronics, Inc., mb91307r Datasheet
mb91307r
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mb91307r Summary of contents
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... DATA SHEET 32-Bit Microcontroller CMOS FR60 MB91307 Series MB91306R/MB91307R DESCRIPTION The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, high-speed CPU processing. External bus access is assumed in order to support the expanded address space accessible by the 32-bit CPU, and a 1K bytes cache memory plus large RAM are provided for high-speed execution of CPU instructions ...
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... RDY input for external wait cycles • DMA supports fly-by transfer with independent I/O wait control Built-in RAM • 128K bytes (MB91307R), 64K bytes (MB91306R) • Accepts writing of data and instruction codes, enabling use as instruction RAM Instruction cache • 1K bytes capacity • ...
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... Gear functions • Built-in time base timer • Packages: LQFP-120 (FPT-120P-M21) : MB91306R, MB91307R • CMOS technology : MB91V307R : 3.3 V ± 0.3 V (built-in regulator 3.3 V → 2.5 V) • Supply voltage : MB91306R, MB91307R : 3.3 V ± 0.3 V, 1.8V ± 0.15 V dual power supplies * : Purchase of Fujitsu components conveys a license under the Philips ...
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MB91307 Series PIN ASSIGNMENT PA3/CS3 61 PA4/CS4 62 PA5/CS5 CCI PA6/CS6 65 PA7/CS7 66 P80/RDY 67 P81/BGRNT 68 P82/BRQ UUB/WR0 71 P85/ULB/WR1 72 NMI CCI INIT 76 P90/SYSCLK ...
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PIN DESCRIPTIONS I/O Pin no. Pin name circuit type D16 to D23 P20 to P27 93 to 100 D24 to D31 C 102 to 109 A00 to A07 F 111 to 118 A08 to A15 F ...
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MB91307 Series I/O Pin no. Pin name circuit type SC0 27 F PI2 SI1 28 F PI3 SO1 29 F PI4 SC1 30 F PI5 SI2 31 F PH0 SO2 32 F PH1 SC2 33 F PH2 TOT0 35 C ...
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I/O Pin no. Pin name circuit type SDA 38 Q PH6 SCL 39 Q PH7 DREQ2 40 F PG0 DACK2 41 F PG1 DEOP2 DSTP2 42 F PG2 MD2 to MD0 G DREQ0 46 F PB0 DACK0 ...
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MB91307 Series I/O Pin no. Pin name circuit type DREQ1 49 F PB3 DACK1 50 F PB4 DEOP1 DSTP1 51 F PB5 IOWR 56 F PB6 IORD 57 F PB7 CS0 58 F PA1 CS1 ...
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I/O Pin no. Pin name circuit type CS4 62 F PA4 CS5 63 F PA5 ⎯ CCI CS6 65 F PA6 CS7 66 F PA7 RDY 67 C P80 BGRNT 68 F P81 BRQ 69 P P82 70 ...
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MB91307 Series (Continued) I/O Pin no. Pin name circuit type 73 NMI CCI 76 INIT B SYSCLK 77 F P90 78 P91 F MCLK 79 F P92 80 P93 LBA F P94 BAA ...
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I/O CIRCUIT TYPE Type STANDBY CONTROL B C STANDBY CONTROL D CONTROL Circuit clock input digital input digital output digital output digital input analog input MB91307 Series Remarks • Oscillator feedback resistance approx. 1 MΩ • CMOS ...
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MB91307 Series Type F STANDBY CONTROL Circuit digital output digital output digital input digital input digital input digital output digital output digital input digital output digital output Remarks • CMOS level output • CMOS level ...
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Type P STANDBY CONTROL Q STANDBY CONTROL Circuit digital output digital output CONTROL digital input Open drain control digital output digital input MB91307 Series Remarks • CMOS level input/output with standby control with pull-down resistance (25 kΩ) • Open ...
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MB91307 Series HANDLING DEVICES MB91307 Series • Preventing Latchup When CMOS integrated circuit devices are subjected to applied voltages higher than V pins (other than medium- and high-withstand voltage pins voltages lower than V in excess of rated ...
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Sample use of Stop Mode with 3.3 V power supply 3.3 V 2.4 k 7.6 k GND • About crystal oscillator circuit Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit ...
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MB91307 Series • Clock control block For L-level input to the INIT pin, allow for the regulator settling time or oscillation settling time. • Bit search module The 0-detection, 1-detection, and transition-detection data registers (BSD0, BSD1, and BSDC) are only ...
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Note : Stop mode (oscillation stop mode) cannot be used. • Low-power consumption modes • To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time-base counter control ...
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MB91307 Series • Terminal and timing control register (TCR) (0x00000683) The terminal and timing control register (TCR write-only register. Therefore, do not access TCR with a bit manipulation instruction. If you intend to disable sharing of the bus ...
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LDUH @ (R14, disp9), Ri ANDH Rj, @Ri EORB Rj, @Ri DMOVB @R13+, @dir8 DMOVB @dir8, @R13+ • When full trace mode is specified as trace mode and the DIVOS and DIV1 instructions are not 4-byte aligned. • Even if ...
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MB91307 Series • RMW instructions using R15 If one of the instructions listed below is executed, the value of SSP or USP* is not used as the value of R15 and result, an incorrect value is written to ...
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Unique to the evaluation chip MB91V307R • Simultaneous occurrences of a software break and a user interrupt/NMI When a software break and a user interrupt /NMI take place at the same time, the emulator debugger can cause the following phenomena: ...
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MB91307 Series • Alignment error (emulator debugger) Assume that instruction alignment error break is enabled and an instruction that causes a wait is executed between an instruction to read a branch destination address from memory and a branch instruction. Under ...
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... BLOCK DIAGRAM Bit search RAM* 32 Adapter Clock control Interrupt controller External interrupt * : Internal RAM 128K bytes for MB91307R CPU Core 32 Instruction 32 cache 1K bytes DMAC Bus Converter 5 channels 32 External 16 memory interface 16 UART U-TIMER 3 channels 3 channels 1 channel Reload A/D timer 4 channels 3 channels 64K bytes for MB91306R ...
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MB91307 Series CPU AND CONTROL BLOCK Internal Architecture The FR series CPU is a high-performance core using RISC architecture with a high-capability instruction set intended for built-in applications. 1. Features • Uses of RISC Architecture Basic instruction set: 1 instruction ...
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Internal Architecture The FR series CPU uses a Harvard architecture with independent instruction bus and data bus. The instruction bus (I-bus) is connected to an on-chip instruction cache. a 32-bit ←→16-bit bus converter is connected to the bus (F-bus) ...
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MB91307 Series 3. Programming Model • Basic Programming Model General-purpose register Program counter Program status Table base register Return pointer System stack pointer User stack pointer Multiplier result registers 26 32 bits R0 R1 R12 AC R13 FP R14 R15 ...
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Registers • General Purpose Register R0 R1 R12 R13 R14 R15 Registers are general-purpose registers. These registers can be used as accumulators for compu- tation operations pointers for memory access. Of the ...
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MB91307 Series • SCR (System Condition code Register) Stepwise division flags These flags store interim data during execution of stepwise division. Step trace trap flag Indicates whether the step trace trap is enabled or disabled. The step trace trap function ...
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RP (Return Pointer The return register stores the address for return from subroutines. During execution of a CALL instruction, the PC value is transferred to this RP register. During execution of a RET instruction, the contents of ...
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MB91307 Series SETTING MODE In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating mode. 1. Mode Pins The three pins MD2, MD1, MD0 are used in mode vector ...
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... H External area FFFF FFFF H addresses) of logical address space with linear access from the CPU. to 0FF 1FF 3FF H H MB91306R MB91306R/MB91307R Internal ROM External bus mode external bus mode I/O I/O I/O I/O Access Access prohibited prohibited Internal RAM 128K bytes External area Access ...
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... MB91307 Series •Use of Built-in RAM The MB91307R contains 128K bytes of internal RAM, and MB91306R contains 64K bytes of internal RAM. To enable use of this RAM, the mode register must be set to internal ROM external bus mode (ROMA=1). Precautions for use of this model • The reset vector is fixed at 000F FFFC • ...
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USER PROGRAM INITIALIZATION The following sequence describes an example using built-in RAM. For the MB91306R, only the internal RAM area is different but the setting is same. 1. Hardware Setting Conditions MB91307 series CS0 A19 Assume that ...
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MB91307 Series 3. User Program Initialization Steps MB91307 series CS0 1) Set the TBR register so that the interrupt table is 001F FFXX includes a chip select setting, and at the same time the CS0 address is set to be ...
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I/O MAP This map shows the correlation between areas of memory space and individual registers in peripheral resources. [How to read the map] Address +0 +1 PDR0 [R/W] PDR1 [R/W] 000000 H XXXXXXXX XXXXXXXX Read/write attributes Register default value after ...
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MB91307 Series Address +0 ⎯ 000000 H ⎯ 000004 H PDR8 [R/W] PDR9 [R/W] 000008 H --X--XXX XXXXXXX- 00000C H PDRG [R/W] PDRH [R/W] 000010 H -----XXX XXX00XXX 000018 H to 00001C H 000020 H to 00003C H EIRR [R/W] ...
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Address +0 +1 UTIM [R] (UTIMR [W] ) 00006C H 00000000 00000000 SSR [R/W] SIDR [R/W] 000070 H 00001-00 XXXXXXXX UTIM [R] (UTIMR [W] ) 000074 H 00000000 00000000 ADCR [R] 000078 H ------XX XXXXXXXX 00007C H 000080 H 000084 ...
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MB91307 Series Address +0 000200 H 00000000 0000XXXX XXXXXXXX XXXXXXXX 000204 H 00000000 00000000 00000000 00000000 000208 H 00000000 0000XXXX XXXXXXXX XXXXXXXX 00020C H 00000000 00000000 00000000 00000000 000210 H 00000000 0000XXXX XXXXXXXX XXXXXXXX 000214 H 00000000 00000000 00000000 00000000 ...
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Address +0 +1 000300 H ⎯ 000304 H 000308 H to 0003E0 H ⎯ 0003E4 H 0003E8 H to 0003EC H BSD0 [W] 0003F0 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] 0003F4 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] 0003F8 ...
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MB91307 Series Address +0 ICR00 [R/W] ICR01 [R/W] 000440 H ---11111 ---11111 ICR04 [R/W] ICR05 [R/W] 000444 H ---11111 ---11111 ICR08 [R/W] ICR09 [R/W] 000448 H ---11111 ---11111 ICR12 [R/W] ICR13 [R/W] 00044C H ---11111 ---11111 ICR16 [R/W] ICR17 [R/W] ...
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Address +0 +1 ⎯ ⎯ 000600 H ⎯ ⎯ 000604 H DDR8 [R/W] DDR9 [R/W] 000608 H --0--000 00000000 00060C H ⎯ ⎯ 000610 H ⎯ ⎯ 000614 H PFR8 [R/W] PFR9 [R/W] 000618 H --1--0-- 1111111- PFRB2 [R/W] 00061C ...
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MB91307 Series Address +0 ASR6 [R/W] 000658 H XXXXXXXX XXXXXXXX ASR7 [R/W] 00065C H XXXXXXXX XXXXXXXX AWR0 [R/W] 000660 H 011111111 11111111 AWR2 [R/W] 000664 H XXXXXXXX XXXXXXXX AWR4 [R/W] 000668 H XXXXXXXX XXXXXXXX AWR6 [R/W] 00066C H XXXXXXXX XXXXXXXX ...
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Address +0 +1 ECNT0 [W] ECNT1 [W] 000B08 H XXXXXXXX XXXXXXXX EWPT [R] 000B0C H 00000000 00000000 EDTR0 [W] 000B10 H XXXXXXXX XXXXXXXX 000B14 H to 000B1C H 000B20 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B24 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ...
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MB91307 Series (Continued) Address +0 000B54 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B58 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B5C H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B60 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B64 H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 000B68 H XXXXXXXX XXXXXXXX XXXXXXXX ...
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INTERRUPT SOURCES AND INTERRUPT VECTORS Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) ...
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MB91307 Series Interrupt source DMAC1(end, error) DMAC2(end, error) DMAC3(end, error) DMAC4(end, error) A System reserved System reserved System reserved System reserved U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow System reserved System reserved System reserved System reserved System ...
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Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instructions Interrupt number Interrupt level Decimal Hex ⎯ ⎯ 70 ...
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MB91307 Series PERIPHERAL RESOURCES 1. Interrupt Controller (1) Overview The interrupt controller receives and processes arbitration of interrupts. •Hardware Configuration This module is configured from the following elements. • ICR register • Interrupt priority determination circuit • Interrupt level and ...
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Register List bit 7 Address : ⎯ 00000440 H Address : ⎯ 00000441 H Address : ⎯ 00000442 H Address : ⎯ 00000443 H Address : ⎯ 00000444 H Address : ⎯ 00000445 H Address : ⎯ 00000446 H ...
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MB91307 Series (Continued) bit 7 Address : ⎯ 00000460 H Address : ⎯ 00000461 H Address : ⎯ 00000462 H Address : ⎯ 00000463 H Address : ⎯ 00000464 H Address : ⎯ 00000465 H Address : ⎯ 00000466 H ...
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Block Diagram UNMI determination RI00 RI47 (DLYIRQ) (“1” when LEVEL ≠ 11111) WAKEUP Determine order of priority 5 NMI processing LEVEL LEVEL, VECTOR ICR00 generation 6 VECTOR determination ICR47 R-bus MB91307 Series LEVEL4 to LEVEL0 HLDREQ MHALTI hold request ...
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MB91307 Series 2. External Interrupt - NMI Control Block (1) Overview The External Interrupt-control block controls external interrupt requests input at the NMI and INT0 to INT7 pins. The request level can be selected from “H,” “L,” “rising edge,” or ...
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REALOS Related Hardware REALOS related hardware is used by the REALOS operating system. Therefore, when REALOS is in use, these resources cannot be used by user programs. • Delay Interrupt Module (1) Overview The delay interrupt module is a ...
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MB91307 Series • Bit Search Module (1) Overview Searches data written to input registers for “0” or “1” or change points, and outputs the value of the detected bits. (2) Register List 31 Address : 000003F0 H Address : 000003F4 ...
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... The input pin (TIN) can be used for event input in external event count mode, and trigger input or gate input in internal clock mode. The external event count function can be used in reload mode frequency multiplier in external clock mode. The MB91306R/MB91307R contain 3 channels ( this timer. (2) Register List • Control status register (TMCSR) 15 ⎯ ...
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MB91307 Series (3) Block Diagram Clock selector 2 φ Internal clock 3 56 16-bit reload register Reload 16-bit down counter 2 OUT GATE CTL. 2 CSL1 CSL0 Re-trigger IN CTL. EXCK 3 φ φ Prescaler ...
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U-TIMER (16 bit timer for UART baud rate generation) (1) Overview The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Any desired baud rate can be set using the combination of chip operating ...
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MB91307 Series 6. UART (1) Overview The UART is an I/O port for asynchronous (start-stop synchronized) or CLK synchronized transmission, providing the following features. This device features a 3-channel built-in UART. • Full duplex double buffer • Asynchronous (start-stop synchronized) ...
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Block Diagram Control signal From U-TIMER Clock select circuit External clock SC SI (receiving data) Receiving status decision circuit DMA receiving error signal (to DMAC) MD1 MD0 SMR register CS0 SCKE SOE TX clock RX clock RX control circuit ...
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MB91307 Series 7. A/D Converter (Sequential comparison type) (1) Overview This A/D converter is a module that coverts analog input voltages to digital values, and provides the following features. • Minimum conversion time • Built-in sample & hold circuit • ...
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Block Diagram Sample & hold circuit Channel decoder Timing generator Clock (CLKP) ATG (External pin trigger) Reload timer ch1 (Internal connection) (4) Precautions for Use: When the A/D converter is started from an external trigger or internal timer, the ...
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MB91307 Series Interface (1) Overview 2 The I C interface operates as a master/slave device on the I following features are provided. • Master/slave sending and receiving • Arbitration function • Clock synchronization function • Slave ...
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Slave Address Mask Register (ITMK) Address : 000098 H ENTB Default value → Address : 000099 H Default value → • 7-Bit Slave Address Register (ISBA) Address : 00009B H Default value → • 7-Bit Slave Address ...
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MB91307 Series (3) Block Diagram ICCR EN IDBL DBL ICCR CS4 CS3 CS2 CS1 CS0 IBSR BB RSC LRB TRX ADT AL IBCR BER BEIE INTE INT IBCR SCC MSS ACK GCAA IBSR AAS GCA ENTB ISMK RAL 64 2 ...
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DMAC (DMA Controller) (1) Overview This module is used to accomplish DMA (Direct Memory Access) transfer on FR family devices. DMA transfer controlled by this module increases system performance by enabling high speed transfer of many types of data ...
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MB91307 Series (2) Register Descriptions ch0 Control/status register A ch0 Control/status register B ch1 Control/status register A ch1 Control/status register B ch2 Control/status register A ch2 Control/status register B ch3 Control/status register A ch3 Control/status register B ch4 Control/status register ...
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Block Diagram DMA transfer request to bus controller Read/write Read control Write DDNO To bus controller Write back Access address Write back Counter DMA start Buffer source selection circuit & request Selector acceptance control DTC two-stage register DTCR Counter ...
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MB91307 Series 10. External Interface (1) Overview The external interface controller controls the interface between the LSI’s internal bus and external memory devices. This section describes the functions of the external interface. (2) Features • ...
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Block Diagram Internal Internal data address bus bus 32 32 Write buffer Read buffer Address buffer ASR ASZ (4) I/O Pins These are the external interface pins. (Some pins have dual functions.) < Normal bus interface > A24 to ...
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MB91307 Series < DMA interface > IOWR, IORD DACK0, DACK1, DACK2 DREQ0, DREQ1, DREQ2 DEOP0/DSTP0, DEOP1/DSTP1, DEOP2/DSTP2 (5) Register List Address 00000640 00000644 00000648 0000064C 00000650 00000654 00000658 0000065C 00000660 00000664 00000668 0000066C 00000670 00000674 00000678 0000067C 00000680 00000684 00000688 ...
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ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Supply voltage* 1 Internal supply voltage Analog supply voltage Analog reference voltage Input voltage* 1 Analog pin input voltage Output voltage* 1 Maximum clamp current Total maximum clamp current L level maximum output ...
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MB91307 Series • Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may ...
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Recommended Operating Conditions Parameter Supply voltage Analog supply voltage Analog reference voltage Operating temperature WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are ...
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MB91307 Series 3. DC Characteristics (V Parameter Symbol V See note * IH “H” level input Input pins voltage V HIS other than * V See note * IL “L” level input voltage Input pins V ILS other than * ...
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AC Characteristics (1) Clock Timing Standards (V CCI Parameter Clock frequency (1) Clock cycle time Clock frequency (2) Clock frequency (3) Clock cycle time Input clock pulse width Input clock rise, fall time Internal operating clock frequency Internal operating ...
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MB91307 Series • Clock timing measurement conditions • Warranted operating range V (V) CC 1.95 1.65 0 0.78 • External/internal clock setting range (MHz CPT f CPP 33 16.5 ...
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Clock Output Timing (V CCI Parameter Symbol Cycle time t CYC MCLK↑→MCLK↓ t CHCL SYSCLK↑→SYSCLK↓ MCLK↓→MCLK↑ t CLCL SYSCLK↓→SYSCLK↑ MCLK, SYSCLK * represents the frequency of one clock cycle including the gear period. CYC *2 ...
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MB91307 Series (3) Reset and Hardware Standby Input Standards (V Parameter Hardware standby input time INIT input time (power-on) INIT input time (other than power-on) HST INIT * : INIT input time (at power-on) FAR, Ceralock : φ × 2 ...
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Normal Bus Access Read/Write Operation (V CCI Parameter Symbol CS0 to CS7 setup t CSLCH CS0 to CS7 hold t CSHCH Address setup t ASCH Address hold t CHAX Valid address → t AVDV valid data input time t ...
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MB91307 Series V OH MCLK, SYSCLK AS LBA CS0 to CS7 A23 to A00 RD D31 to D16 WR0 to WR1 D31 to D16 80 t CYC BA1 ASLCH CSLCH V OL ...
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Ready Input Timing = 1. 1. CCI Parameter Symbol RDY setup time → t RDYS MCLK↑, SYSCLK↑ MCLK↑, SYSCLK↑ t RDYH RDY hold time MCLK, SYSCLK t CHASL RDY Wait applied RDY Wait not ...
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MB91307 Series (6) Hold Timing (V Parameter Symbol t CHBGL BGRNT delay time t CHBGH Pin floating t → BGRNT↓time BGRNT↑ → valid time t Note: After a BRQ is accepted, a minimum of 1 cycle is required before BGRNT ...
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UART Timing (V CCI Parameter Symbol Pin name Serial clock cycle time SCLK↓ → SOUT delay time Valid SIN → SCLK↑ SCLK↑ → valid SIN hold time Serial clock “H” pulse width Serial clock “L” pulse width SCLK↓ → ...
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MB91307 Series (8) Timer Clock Input Timing (V Parameter Symbol Input pulse width Note the cycle time of the peripheral system clock. CYCP TIN0 to TIN2 (9) Trigger Input Timing (V Parameter A/D startup trigger input time Note: ...
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DMA Controller Timing = 1. 1. CCI Parameter Symbol DREQ input pulse width t DRWH DSTP input pulse width t DSWH t CLDL DACK delay time t CLDH t CLEL DEOP delay time t ...
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MB91307 Series MCLK SYSCLK DACK0 to DACK2 DEOP0 to DEOP2 IORD IOWR DREQ0 to DREQ2 DSTP0 to DSTP2 86 t CYC BA1 BA2 CLDL CLEL ...
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I C Timing = 1. 1. CCI Parameter SCL clock frequency (Repeat) “start” condition hold time SDA ↓ → SCL ↓ SCL clock “L” width SCL clock “H” width Repeat “start” condition setup ...
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... AVss ⎯ ⎯ ⎯ AVRH ⎯ ⎯ ⎯ AN0 to AN3 = 1. 1.95 V machine clock 33 MHz. CCI R Comparator C MB91307R/306R MB91V307R = °C to +70 ° Value Typ Max 10 10 ⎯ ± 4.5 ⎯ ± 3.0 ⎯ ± 2.5 + 0.5 + 4.5 ⎯ ⎯ 1 ...
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... If the sampling time cannot be sufficient, connect a capacitor of about 0 the analog input pin. • About errors As | AVRH | becomes smaller, values of relative errorsgrow larger. External impedance = 0 kΩ kΩ MB91V307R MB91307 Series MB91307R MB91306R Minimum sampling time [µs] 89 ...
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MB91307 Series Definition of A/D Converter Terms • Resolution Indicates the ability of the A/D converter to discriminate analog variation • Linear error Expresses the deviation between actual conversion characteristics and a straight line connecting the device’s zero transition point ...
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Total error Expresses the difference between actual and theoretical values as error, including zero transition error, full- scale error, and linearity error. 3FF H 3FE H {1 LSB × (N − 0.5 LSB 3FD H 004 H ...
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MB91307 Series EXAMPLE CHARACTERISTICS (1) Sample output voltage characteristics (T Sample output H voltage (V OH 3.6 3.4 3.2 3.0 2.8 3.0 3.2 3.4 Supply voltage (V) (2) Sample input voltage characteristics (T Sample input H/L level characteristics (CMOS) 3.0 ...
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Sample sleep current (I ) characteristics CCS = +25 °C, 33 MHz 3.0 3.2 3.4 3.6 Supply voltage (V) Sample A/D supply current (I ) characteristics A = +25 °C, 33 MHz) (T ...
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... MB91307 Series ORDERING INFORMATION Part number MB91306RPFV MB91307RPFV MB91V307RCR 94 Package 120-pin, Plastic LQFP Lead-free package (FPT-120P-M21) 135-pin, Ceramic PGA For development tool use (PGA-135C-A02) Remarks ...
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PACKAGE DIMENSION 120-pin, Plastic LQFP (FPT-120P-M21) 18.00±0.20(.709±.008)SQ +0.40 +.016 * 16.00 .630 –0.10 –.004 90 91 INDEX 120 LEAD No. 1 0.22±0.05 0.50(.020) (.009±.002) 2002 FUJITSU LIMITED F120033S-c-4-4 C Note These dimensions do not include resin protrusion. ...
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MB91307 Series FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, ...