tc90a58f TOSHIBA Semiconductor CORPORATION, tc90a58f Datasheet
tc90a58f
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tc90a58f Summary of contents
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... Preliminary TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic 3-Channel AD Converter The TC90A58F is a 3-channel AD converter for video applications which incorporates a clamp circuit. The 10-bit converter can be used as either an 8-bit 3-channel AD converter 10-bit 2-channel AD converter. Main Functions and Features · 3-channel, 8-bit AD converter (input amplitude: 1. and and B inputs. · ...
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... BIAS ADCLAMP RESN Sync/Clamp Pulse Generator CLAMP HDIN VDIN CCIR601/656 Cb/Cr Delay Cb & Format Digital Filters HPLL HREF CKSEL[3:0] EXTCLK BFIL LFIL 2 TC90A58F Y/Cb/ ROUT[7:0] Format 8 Cb/ GOUT[7:0] 8 BOUT[7:0] 8 VDOUT HDOUT APCLK Bus TES[2:0] SCK SDA 2002-02-06 ...
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... VRB_Q 11 AVDD 12 AIN_Q 13 AVSS 14 VRT_Q 15 PVDD 16 APCLK 17 PVSS 18 LFIL 19 BFIL TC90A58F TC90A58F 60 ROUT7 59 ROUT6 58 ROUT5 ROUT4 57 56 ROUT3 55 ROUT2 54 ROUT1 53 ROUT0 52 DVSS 51 GOUT7 GOUT6 50 49 GOUT5 48 GOUT4 ...
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... Outputs vertical sync signal pulse. Pulse polarity can be set using I Outputs horizontal sync signal pulse. Pulse polarity can be set using I Internal, for output PAD Internal, for output PAD 4 TC90A58F Notes ¾ ¾ ¾ ¾ ¾ according to p-p ¾ ...
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... For AD digital block Ground to AVSS (pin 69) via 0.1-mF capacitor. Ground to AVSS (pin 69) via 0.1-mF capacitor. Connect 0.47-mF capacitor and 20-W resistor. Ground to AVSS (pin 69) via 0.1-mF capacitor. AD reference resistance: Connect 8.2-kW resistor. Connect other end of resistor to analog power supply. 5 TC90A58F Notes ¾ ¾ ¾ ¾ ¾ bus register. ...
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... Functions 1. Low-Pass Filter (LPF) TC90A58F incorporates a low-pass filter (-3dB) for Y and C signals. When the system clock is 27 MHz, cut-off frequency is 6 MHz for Y signal and 2.8 MHz for C signal. When the system clock frequency is higher than 27 MHz, cut-off frequencies are determined as follows: Example: System clock frequency = 29 ...
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... C bus register Sub-Address 00H 7-0 7-0 7-0 Cb2 Cr2 Cb4 7-0 7-0 7-0 7-0 Hi 7-0 7-0 7-0 Cb2 Cr3 Cb4 7-0 7-0 7-0 7-0 Hi 7-0 7-0 7-0 Cb2 Cb3 Cb4 7-0 7-0 7-0 7-0 Cr2 Cr3 Cr4 7-0 7-0 7-0 7-0 7 TC90A58F May 10 1999 12M [freq: Hz 7-0 7-0 7-0 Cr4 Cb6 Cr6 7-0 7-0 7 7-0 7-0 7-0 Cr5 Cb6 Cr7 7-0 7-0 7 7-0 7-0 7-0 Cb5 Cb6 Cb7 7-0 7-0 7-0 Cr5 Cr6 Cr7 7-0 7-0 7-0 2002-02-06 ...
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... Cb0 Cr2 Cr2 7-6 3-2 7-6 Cb0 Cr2 Cr2 5-4 1-0 5-4 Hi-Z TRG Hi 7-0 7-0 7-0 Cb2 Cr2 Cb4 7-0 7-0 7-0 7-0 Hi-Z Cr0 Y1 Cb2 7-0 7-0 7-0 Hi-Z Hi bus register Sub-Address 17H bus register Sub-Address 2AH. 8 TC90A58F 7-0 7-0 7-0 Cb4 Cb4 Cb4 7-6 5-4 3-2 Cr4 Cr4 Cr4 7-6 5-4 3 7-0 7-0 7-0 Cb4 Cb4 Cb6 3-2 7-6 3-2 Cb4 Cb4 Cb6 1-0 5-4 1 7-0 7-0 7-0 Cr4 Cb6 ...
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... Variable (set using I When VDSEL = 0, VDSOFF = 0 and VRNMOD = 0, VD input from VDIN is output, delayed by 15 clocks. With all other settings, VDOUT changes with the same timing as HDOUT. Figure 4 VDOUT Timing Chart 9 TC90A58F 2 C bus registers (see figure below bus register) 2 ...
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... In ITU-R656 Mode only, SAV and EAV (H, V and F information) are multiplexed in the data. Where data is multiplexed depends on the HD output timing Bus The TC90A58F bus control format conforms to the Philips I The two least significant bits (A0 and A1) of the slave address can be set using TES1 and TES0 (pins 79 and 80). Slave Address A6 ...
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... SS AVDD AVSS 13. 10-Bit ADC The TC90A58F can also be used as a 10-bit AD converter. This setting can be made using the M10B bit in 2 the I C bus register Sub-Address 1CH. Note that when the device is used as a 10-bit AD converter, only two channels (the Y and Cb signals) are output from the following output pins ...
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... Y (RGB): 16 (for 8-bit conversion) C: 128 (for 8-bit conversion) 15. ADC Input Signal The input signal band and range are as follows: Band: 10 MHz Range: 1.32 V (typ.), 0.99 V p-p 16. 5-V Withstanding Voltage HDIN, VDIN, SDA and SCL (pins 24, 25, 27 and 28) have a withstanding voltage ~2.31 V p-p p-p 12 TC90A58F 2002-02-06 ...
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... I C Bus Register Map 1. Format The TC90A58F bus control format conforms to the Philips I Data transfer format S Slave address bits MSB MSB (1) Start and stop conditions SDA SCL (2) Bit transfer SDA SCL (3) Acknowledgement SDA from master SDA from slave SCL from master ...
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... DIVIIC0 DIVHDSEL REG6 REG10 LPI0ON2 LPI0ON1 LPI0ON0 REG8 QDSEL1 * * * REGSWG7 REGSWG3 REGSWG1 * * CKOUTSTP * * * 14 TC90A58F ¾ Patent Right to use these 2 C Standard Specification as defined by Bit 3 Bit 2 Bit 1 MODE0 RGBC VLINSEL OUTSEL CLKSEL HDPQO VDPQO HDPOL HDPO HDDIRECT HRTMG4 HRTMG3 HDSTA8 HDSTA7 ...
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... HDSELB: Switches HD output signal. 0 (default): Variable HD output timing MODE2 MODE1 MODE0 PAL MODE0 Output Format 0 4:2:2 (standard, default) 1 4:2:2 (special) 0 4:1:1 (standard) 1 4:1:1 (special) 0 4:4:4 1 R601 16-Bit Mode 0 R601 8-Bit Mode 1 R656 1: Fixed HD output timing 15 TC90A58F (LSB) RGBC VLINSEL HDSELB 2002-02-06 0 ...
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... CKPOL: Switches the polarity of output clock (APCLK and CKOUT). 0 (default): Positive polarity PCSEL1 DIVSEL HPLLSTOP PCSEL1 PC Used 0 PC2 (default) 0 Use prohibited 1 Use prohibited 1 PC3 1: HPLL stops oscillating. 1: 1-V p-p 1: Negative polarity 16 TC90A58F (LSB) OUTSEL CLKSEL CKPOL output 2002-02-06 0 ...
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... HDPOL: Switches the HPLL HD input polarity. · 0 (default): Same polarity as the input VRNMOD VCNTCR HDPQO DAC power-down OFF 1 (default): ADC power-down OFF 1: Opposite polarity from the input HD 17 TC90A58F (LSB) VDPQO HDPOL 2002-02-06 ¾ ¾ ...
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... HRTMG10 in Sub-Address 03H and HRTMG1~HRTMG0 in Sub-Address 05H VNSOFF VDPO VDDIRECT Disables VD input. 1: Opposite polarity 1: Opposite polarity HRTMG7 HRTMG6 HRTMG5 TC90A58F (LSB) HDPO HDDIRECT HRTMG10 (LSB) HRTMG4 HRTMG3 HRTMG2 2002-02- ...
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... HDSTA0 HDPW5 HDPW4 HDPW3 VRTMG8 VRTMG7 VRTMG6 bus data is updated continuously or at the VD cycle. 19 TC90A58F (LSB) HDSTA7 HDSTA6 HDSTA5 (LSB) HDPW10 HDPW9 HDPW8 (LSB) HDPW2 ...
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... This setting works in combination with the setting of CLPSTA3~CLPSTA0 in Sub-Address 0DH VRTMG0 VDOSEL VDOSELGT CLPSTA9 CLPSTA8 CLPSTA7 Does not invert polarity. 20 TC90A58F (LSB) VGSTA REGF1 REGF2 (LSB) CLPSTA6 CLPSTA5 CLPSTA4 2002-02-06 ...
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... CLPWID3 CLPWID2 Internally generated clamp pulse ¾ ¾ VGTEDA9 VGTEDA8 ¾ ¾ VGTEDA2 VGTEDA1 VGTEDA0 TC90A58F (LSB) CLPWID9 CLPWID8 CLPWID7 (LSB) CLPWID1 CLPWID0 CLPSEL (LSB) VGTEDA7 ...
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... VGTEDB4 VGTEDB3 VGTEDB2 ODEV9 ODEV8 ODEV7 ODEV1 ODEV0 ODDETPO Inverted 22 TC90A58F (LSB) VGTEDB1 VGTEDB0 VGATEO (LSB) ODEV6 ODEV5 ODEV4 (LSB) ¾ ¾ ¾ ¾ ...
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... MHz ¾ ¾ 13.5 MHz 23 TC90A58F (LSB) ¾ HRESVAR ¾ Horizontal Frequency 31.5 kHz, 480P 33.7 kHz, 1080I 45.0 kHz, 720P 31.5 kHz 15.7 kHz, 480I ¾ ¾ 15.7 kHz, general-purpose External clock input ¾ ¾ ...
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... YDLY3~YDLY0: Sets Y delay. YDLY3 0 0 ¾ REG6 REG10 YDLY2 YDLY1 YDLY0 clocks clock ¾ ¾ ¾ clocks clocks Invalid 24 TC90A58F YDLY3 YDLY2 YDLY1 Delay 2002-02-06 0 (LSB) YDLY0 0 ...
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... The Cb signal passes through the LPF circuit but the filter is not ON (9-clock delay is added). Filter ON (6 MHz) (9-clock delay is added) Invalid Filter ON (2.8 MHz) (9-clock delay is added) The Cb signal bypasses the LPF circuit (1-clock delay is added) Invalid 25 TC90A58F (LSB) LPQ0ON2 LPQ0ON１ LPQ0ON0 ...
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... Sampling Using 1/2 the Main Sampling Using 1/4 the Main Clock Cb0, Cb2, Cb4, … Cb0, Cb4, Cb8, … Cb1, Cb3, Cb5, … Cb1, Cb5, Cb9, … Cb2, Cb6, Cb10, … Unused Cb3, Cb7, Cb11, … Unused 26 TC90A58F (LSB) IDSEL1 IDSEL0 LPYON Clock ...
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... Input and output settings depend on test mode. 1: Forces HDOUT and VDOUT to Input Mode ¾ ¾ ¾ ¾ ¾ ¾ TC90A58F (LSB) ¾ ¾ ¾ ¾ ¾ ¾ (LSB) REGSWB6 REGSWH 2002-02-06 ¾ ...
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... Sets Y, Cb and Cr signal output to internal color bar signal output ¾ ¾ CKOUTSTP ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 28 TC90A58F (LSB) ¾ ¾ ¾ ¾ ¾ ¾ (LSB) ¾ ¾ BAR ¾ ¾ ...
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... Operating temperature Symbol Rating + 1923 D -55 to 125 T stg 1923 962 25 75 Ambient temperature (°C) Symbol Min Typ. Max V 3.0 3.3 3.6 DD ¾ -20 ¾ opr 29 TC90A58F Unit °C 125 Unit V V °C 2002-02-06 ...
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... Output load = 30 pF EXTCLK input, ¾ Duty = 50%, t data4 Output load = 30 pF ¾ ¾ t pd1 ¾ ¾ t pd2 ¾ ¾ t pd3 ¾ ¾ t pd4 30 TC90A58F Min Typ. Max ¾ ¾ 200 ¾ ¾ ¾ 2.4 ¾ ¾ ¾ 2.65 ¾ ¾ ¾ 0.9 ¾ ¾ ¾ 0.65 -10 ¾ ...
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... VDOUT) Figure 7 Phase Difference between Clock and Data Output bus register (min)~9 ns (max) t data1 t data2 = 0 ns (min)~7 ns (max) t data2 t data3 = -18 ns (min)~-9 ns (max) t data3 t data4 = -18 ns (min)~-10 ns (max) t data4 31 TC90A58F 2 C bus register) 2002-02-06 ...
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... VDOUT) Figure 8 Output Signal Delay Time Note7: When the clock duty (TC90A58F internal clock duty) changes, the output signal delay times t (when CKPOL = 1) change only by CKOUT output delay. Thus, the phase difference between CKOUT and the data changes by the change in the CKOUT output delay. ...
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... Times 15.75 1896 31.5 948 33.7 880 45 660 15.734 1716 15.625 1728 33 TC90A58F = = = = 3 25° ° ° ° C) VDD Min Typ. Max Unit ¾ ¾ 1.32 V p-p ¾ ¾ 30 MHz ¾ ¾ 10 MHz 10-bit conversion ¾ ±1.5 ¾ ...
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... ROUT7 ROUT6 ROUT5 ROUT4 ROUT3 ROUT2 ROUT1 ROUT0 GOUT7 TC90A58F GOUT6 GOUT5 GOUT4 GOUT3 GOUT2 GOUT1 GOUT0 CKOUT TC90A58F DVSS DVSS 43 42 DVDD 41 ...
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... Package Dimensions Weight: g (typ.) 35 TC90A58F 2002-02-06 ...
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... TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 36 TC90A58F 000707EBA 2002-02-06 ...