ak5700 AKM Semiconductor, Inc., ak5700 Datasheet

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ak5700

Manufacturer Part Number
ak5700
Description
16-bit ?? Mono Adc With Pll & Mic-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ak5700VN-L
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AKM
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ASAHI KASEI
The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto
Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports
base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5700 is available in a
24pin QFN, utilizing less board space than competitive offerings.
MS0569-E-01
1. Resolution: 16bits
2. Recording Function
3. Sampling Rate:
4. PLL Input Clock:
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s complement
7. μP I/F: 3-wire Serial
8. Power Supply:
9. Power Supply Current: 6mA
10. Ta = −30 ∼ 85°C
11. Package: 24pin QFN (4mm x 4mm)
12. Pin and Register compatible with AK5701 Stereo Version
- Input Selector
- Full-differential or Single-ended Input
- MIC Amplifier (+30dB/+15dB or 0dB)
- Input Voltage: 1.8Vpp@AVDD=3.0V (= 0.6 x AVDD)
- ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB
- Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
- Digital ALC (Automatic Level Control)
- PLL Slave Mode (EXLRCK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (EXBCLK pin): 7.35kHz ∼ 48kHz
- PLL Slave Mode (MCKI pin):
- PLL Master Mode:
- EXT Slave Mode:
- MCKI pin:
- EXLRCK pin: 1fs
- EXBCLK pin: 32fs/64fs
- DSP Mode, 16bit MSB justified, I
- AVDD: 2.4 ∼ 3.6V
- DVDD: 1.6 ∼ 3.6V
27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz,
11.2896MHz
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
16-Bit ΔΣ Mono ADC with PLL & MIC-AMP
S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB
S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB
GENERAL DESCRIPTION
FEATURES
- 1 -
2
S
AK5700
[AK5700]
2006/12

Related parts for ak5700

ak5700 Summary of contents

Page 1

... The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5700 is available in a 24pin QFN, utilizing less board space than competitive offerings. ...

Page 2

... AIN1/AIN+ S AIN− AIN2 MPWR VCOM AVDD AVSS VCOC PLL MCKO MCKI MS0569-E-01 ALC Audio I/F or ADC HPF Controller IVOL Control Register CSP CSN CCLK CDTI Figure 1. Block Diagram - 2 - [AK5700] DVDD DVSS PDN LRCK BCLK S SDTO E L EXLRCK EXBCLK EXSDTI 2006/12 ...

Page 3

... ASAHI KASEI Ordering Guide −30 ∼ +85°C AK5700VN AKD5700 Evaluation board for AK5700 Pin Layout 19 MPWR 20 TEST 21 AIN2 22 AIN - 23 AIN1 / AIN+ 24 VCOC Comparison with AK5701VN Function ADC channel Number Input Selector Audio I/F Format MS0569-E-01 24pin QFN (0.5mm pitch AK5700VN 10 9 Top View ...

Page 4

... MPWR, VCOC, AIN1/AIN+, AIN−, AIN2 BCLK, LRCK, SDTO, MCKO Digital MCKI, EXBCLK, EXLRCK, EXSDTI MS0569-E-01 PIN/FUNCTION Function (MDIF1 bit = “0”: Single-ended Input) (MDIF1 bit = “1”: Full-differential Input) Setting These pins should be open. These pins should be open. These pins should be connected to DVSS [AK5700] 2006/12 ...

Page 5

... AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0569-E-01 ABSOLUTE MAXIMUM RATINGS Symbol min −0.3 AVDD −0.3 DVDD ΔGND IIN −0.3 VINA −0.3 VIND −30 Ta −65 Tstg Symbol min AVDD 2.4 DVDD 1 [AK5700] max Units 4 0.3 V ± AVDD+0.3 V DVDD+0.3 V °C 85 °C 150 typ Max Units 3.0 3 ...

Page 6

... Bypass Mode (THR bit = “1”, PMADC = M/S bits = “0”), fs=8kHz: AVDD=1μA(typ), DVDD=150μA(typ). Note 13. All digital input pins are fixed to DVDD or DVSS. MS0569-E-01 ANALOG CHARACTERISTICS Min 2.02 1.0 - MGAIN=+15dB, IVOL=0dB, ALC=OFF - - 0.27 1. [AK5700] Typ max Units 60 80 kΩ kΩ + + 0.37 Vpp - 0.066 Vpp 2.25 2 ...

Page 7

... Symbol min 25 Δ CHARACTERISTICS Symbol min VIH 70%DVDD VIH 80%DVDD VIH 90%DVDD VIL - VIL - VIL - VOH DVDD−0.2 VOL - Iin - - 7 - [AK5700] typ max Units - 17.4 kHz 20.0 - kHz 21.1 - kHz - - kHz ±0 1/fs μ 3 typ max Units - - ...

Page 8

... Duty 45 tBCK 1/(64fs) tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK fs 7.35 tLRCKH tBCK−60 Duty 45 tBCK 1/(64fs) tBCKL 0.4 x tBCK tBCKH 0.4 x tBCK - 8 - [AK5700] typ max Units - 27 MHz - - 12.288 MHz kHz tBCK - 1/(32fs ...

Page 9

... Duty - 50 tBCK - 1/(32fs) tBCK - 1/(64fs) dBCK - [AK5700] max Units 48 kHz 1/fs − tBCK 12.288 MHz 13.312 MHz 13.312 MHz - kHz 26 kHz 13 kHz 1/fs − tBCK ns 55 ...

Page 10

... S) −40 tMBLR −70 tLRD −70 tBSD tLRB 50 tBLR 50 tLRD - tBSD - - 10 - [AK5700] typ Max Units 0.5 x tBCK + 40 ns 0.5 x tBCK + ...

Page 11

... PMADC “↑” to SDTO valid (Note 21) HPF1-0 bits = “00” HPF1-0 bits = “01” HPF1-0 bits = “10” Note 20. The AK5700 can be reset by the PDN pin = “L”. Note 21. This is the count of LRCK “↑” from the PMADC bit = “1”. MS0569-E-01 Symbol ...

Page 12

... Duty = tLRCKH 100 tLRCKL 100 tBCK tBCKH tBCKL dBCK = tBCKH / tBCK x 100 1/fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tBCK tDBF dBCK tBSD MSB - 12 - [AK5700] VIH VIL 50%DVDD 50%DVDD tBCKL / tBCK x 100 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 2006/12 ...

Page 13

... Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”) LRCK tMBLR BCLK SDTO Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode) MS0569-E-01 tLRCKH tBCK tDBF dBCK tBSD tBCKL tLRD tBSD - 13 - [AK5700] 50%DVDD 50%DVDD 50%DVDD MSB 50%DVDD 50%DVDD 50%DVDD 50%DVDD 2006/12 ...

Page 14

... Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 1) MS0569-E-01 1/fs tLRCKH tBLR tBCK tBCKH tBCKL 1/fs tLRCKH tBLR tBCK tBCKH tBCKL - 14 - [AK5700] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 2006/12 ...

Page 15

... Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0) MS0569-E-01 1/fCLK tCLKL 1/fs tLRCKL Duty = tLRCKH 100 = tLRCKL 100 tBCK tBCKL fMCK tMCKL dMCK = tMCKL x fMCK x 100 tLRCKH tLRB tBSD MSB - 15 - [AK5700] VIH VIL VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL VIH VIL 50%DVDD 2006/12 ...

Page 16

... EXBCLK Figure 11. Clock Timing (EXT Slave mode) MS0569-E-01 tLRCKH tBSD 1/fCLK tCLKH tCLKL 1/fs Duty = tLRCKH 100 tLRCKH tLRCKL tLRCKL 100 tBCK tBCKH tBCKL - 16 - [AK5700] VIH VIL VIH VIL VIH VIL MSB 50%DVDD VIH VIL VIH VIL VIH VIL 2006/12 ...

Page 17

... ASAHI KASEI EXLRCK tBLR EXBCLK tLRD SDTO Figure 12. Audio Interface Timing (PLL/EXT Slave mode) MS0569-E-01 tLRB tBSD MSB - 17 - [AK5700] VIH VIL VIH VIL 50%DVDD 2006/12 ...

Page 18

... Figure 13. WRITE Command Input Timing (CSP pin = “L”) CSN CCLK CDTI D2 Figure 14. WRITE Data Input Timing (CSP pin = “L”) MS0569-E-01 tCSS tCCKL tCCKH tCCK tCDS tCDH C1 C0 tCSH [AK5700] VIH VIL VIH VIL VIH R/W VIL tCSW VIH VIL VIH VIL VIH VIL 2006/12 ...

Page 19

... Figure 15. WRITE Command Input Timing (CSP pin = “H”) CSN CCLK CDTI D2 Figure 16. WRITE Data Input Timing (CSP pin = “H”) MS0569-E-01 tCSS tCCKL tCCKH tCCK tCDS tCDH C1 C0 tCSH [AK5700] VIH VIL VIH VIL VIH R/W VIL tCSW VIH VIL VIH VIL VIH VIL 2006/12 ...

Page 20

... ASAHI KASEI PMADC bit SDTO PDN MS0569-E-01 tPDV Figure 17. Power Down & Reset Timing 1 tPD Figure 18. Power Down & Reset Timing [AK5700] 50%DVDD VIL 2006/12 ...

Page 21

... The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK5700 is power-down mode (PDN pin = “L”) and exits reset state, the AK5700 is slave mode. After exiting reset state, the AK5700 goes to master mode by changing M/S bit = “1”. ...

Page 22

... When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK5700 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = “0” → “1”) or sampling frequency changes. ...

Page 23

... Output Invalid “L” Output See Table 9 MCKO pin MCKO bit = “0” “1” “L” Output “L” Output “L” Output - 23 - [AK5700] Range Default N/A BCLK pin LRCK pin “L” Output “L” Output Invalid Invalid See Table 10 1fs Output “ ...

Page 24

... DSP or μP 256fs/128fs/64fs/32fs MCLK 32fs, 64fs BCLK 1fs LRCK SDTI Figure 19. PLL Master Mode PS1 bit PS0 bit MCKO pin 0 0 256fs 0 1 128fs 1 0 64fs 1 1 32fs BCLK Output BCKO0 bit Frequency 0 N/A 1 32fs 0 64fs 1 N [AK5700] Default Default 2006/12 ...

Page 25

... The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation (PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADC bit = “ ...

Page 26

... The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation (PMADC bit = “1”). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADC bit = “ ...

Page 27

... EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”) The AK5700 becomes EXT Master Mode by setting as Figure 45. Master clock is input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (see Table 12) ...

Page 28

... SDTO EXSDTI Figure 24. Bypass Mode AK5700 ≥ 32fs BCLK EXBCLK LRCK EXLRCK SDTO AIN Analog In Figure 25. Slave & Bypass Mode - 28 - [AK5700] Mode Figure Power down Default Slave mode Power down Master mode Bypass mode Figure 24 Figure 25 N/A Master mode DSP or μP BCLK ...

Page 29

... This offset can be removed by adding the offset of “128” to 16-bit data before converting to 8-bit data. MS0569-E-01 SDTO BCLK, EXBCLK DSP Mode 0 32fs Reserved ≥ 32fs MSB justified 2 ≥ 32fs I S compatible Table 15. Audio Interface Format Audio Interface Format Table 16. Audio Interface Format in Mode [AK5700] Figure See Table Figure 30 Figure 31 Default 2006/12 ...

Page 30

... 1/ 1/ [AK5700 1/ 1/ ...

Page 31

... S, M/S = “0” or “1” [AK5700 ...

Page 32

... MIC/LINE Input Selector The AK5700 has input selector. When MDIF1 bit is “0”, AIN bit selects AIN1or AIN2. When MDIF1 bit is “1”, AIN1pin become AIN+ pin . In this case, full-differential input is available (Figure 33). When full-differential input is used, the signal should not be input to the pins marked by “X” in Table 19. ...

Page 33

... Figure 33. Connection Example for Full-differential Mic Input (MDIF1bit = “1”) MIC Gain Amplifier The AK5700 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 20). The typical input impedance is 60kΩ(typ)@MGAIN1-0 bits = “00” or 30kΩ(typ)@MGAIN1-0 bits = “01” or “ ...

Page 34

... Table 23. ALC Limiter ATT Step Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms - 34 - [AK5700] Default 0.375dB Default 0.750dB 1.500dB 3.000dB 0.375dB 44.1kHz 2.9ms Default 5.8ms 11.6ms 23.2ms 2006/12 ...

Page 35

... RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 26. ALC Recovery GAIN Step GAIN(dB) Step +36.0 +35.625 +35.25 : +30.375 0.375dB +30.0 +29.625 : −53.25 −53.625 −54.0 MUTE - 35 - [AK5700] 44.1kHz 2.9ms Default 5.8ms 11.6ms 23.2ms Default Default 2006/12 ...

Page 36

... Limiter = Zero crossing Enable Recovery Cycle = 16ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = −4.1dBFS ALC bit = “1” * The value of IVOL should be the same or smaller than REF’ [AK5700] fs=44.1kHz Data Operation −4.1dBFS 01 0 Enable 10 11 ...

Page 37

... If IVL7-0 bits are written during PMADC bit = “0”, IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADC bit is changed to “1”. IVL7-0 F1H F0H EFH : 92H 91H 90H : 03H 02H 01H 00H MS0569-E-01 GAIN (dB) Step +36.0 +35.625 +35.25 : +0.375 0.375dB 0.0 −0.375 : −53.25 −53.625 −54 MUTE Table 29. Input Digital Volume Setting - 37 - [AK5700] Default 2006/12 ...

Page 38

... ALC bit = “0”. System Reset Upon power-up, the AK5700 should be reset by bringing the PDN pin = “L”. This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from “0” to “1”. The initialization cycle time is 3088/fs=70.0ms@fs=44.1kHz when HPF1-0 bits are “ ...

Page 39

... READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address R “1” READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1” Register Address - 39 - [AK5700] 2006/12 ...

Page 40

... IVL6 IVL5 IVL4 REF6 REF5 REF4 ZELMN LMAT1 LMAT0 TE2 TE1 TE0 [AK5700 PMADC PMVCM PLL1 PLL0 M/S PMPLL 0 MDIF1 0 AIN 0 0 MGAIN1 MGAIN0 MSBS BCKP DIF1 DIF0 FS3 FS2 FS1 FS0 ...

Page 41

... Slave Mode (Default) 1: Master Mode PLL3-0: PLL Reference Clock Select (See Table 4) Default: “1001”(MCKI pin=12MHz) MS0569-E- PLL3 PLL2 PLL1 [AK5700 PMVCM 0 PMADC PLL0 M/S PMPLL 2006/12 ...

Page 42

... PMMP [AK5700 MDIF1 0 AIN MGAIN1 MGAIN0 MSBS BCKP DIF1 DIF0 2006/12 ...

Page 43

... D4 HPF0 BCKO1 BCKO0 IVL6 IVL5 IVL4 [AK5700 FS3 FS2 FS1 FS0 THR MCKO PS1 PS0 IVL3 IVL2 IVL1 IVL0 ...

Page 44

... REF6 REF5 REF4 ZELMN LMAT1 LMAT0 [AK5700 ZTM1 ZTM0 WTM1 WTM0 REF3 REF2 REF1 REF0 LMTH1 LMTH0 RGAIN1 RGAIN0 ...

Page 45

... The write operation to TMASTER bit is enabled when TE3-0 bits = “0101”. 0: Except EXT Master Mode (Default) 1: EXT Master Mode MS0569-E- TE3 TE2 TE1 TE0 [AK5700 TMASTER 2006/12 ...

Page 46

... All digital input pins should not be left floating. - When the AK5700 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK5700 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. 0 parallel with Cp+Rp improves PLL jitter characteristics. ...

Page 47

... All digital input pins should not be left floating. - When the AK5700 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed. - When the AK5700 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4. 0 parallel with Cp+Rp improves PLL jitter characteristics. ...

Page 48

... If AVDD and DVDD are supplied separately, the power-up sequence is not critical. AVSS and DVSS of the AK5700 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. ...

Page 49

... PLL operation starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source. PLL lock time is 40ms(max) at MCKI=12MHz (Table 4). (6) The AK5700 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation starts. ...

Page 50

... Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...

Page 51

... EXLRCK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...

Page 52

... EXBCLK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5700. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” VCOM should first be powered up before the other block operates. ...

Page 53

... LRCK pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows. (2a) M/S bit = “1”, setting of FS3-0 and BCKO1-0 bits. (2b) Setting of DIF1-0 bits. ...

Page 54

... Internal Clock <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5700. (2) THR bit should be set to “1” and DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = “0” ...

Page 55

... EXBCLK pin EXSDTI pin <Example> (1) After Power Up: PDN pin “L” “L” time of 150ns or more is needed to reset the AK5700. (2) THR bit should be set to “1”. (3) After EXLRCK, EXBCLK and EXSDTI are input, LRCK, BCLK and SDTO start to output. MS0569-E-01 (1) Power Supply & PDN pin = “L” ...

Page 56

... Registers set-up sequence at ALC operation”. At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK5700 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 12H&13H) ...

Page 57

... Sampling Frequency: 44.1kHz (1) Addr:11H, Data:10H (2) Addr:16H, Data:00H (3) Stop an external MCKI Figure 49. Clock Stopping Sequence (1) Example Audio I/F Format : I2S PLL Reference clock: EXBCLK BCLK frequency: 64fs Sampling Frequency: 44.1kHz Figure 50. Clock Stopping Sequence ( [AK5700] (1) Addr:11H, Data:0CH (2) Stop the external clocks 2006/12 ...

Page 58

... Figure 52. Clock Stopping Sequence (4) Example Audio I/F Format :I2S Input MCKI frequency:256fs "H" or "L" Sampling Frequency:44.1kHz "H" or "L" Figure 53. Clock Stopping Sequence ( [AK5700] (1) Addr:11H, Data:10H (2) Addr:16H, Data:00H (3) Stop the external clocks (1) Stop the external clocks (1) Stop MCKI 2006/12 ...

Page 59

... Power supply current is typ. 20μA by stopping clocks and setting PMVCM bit = “0” after all blocks except for VCOM are powered-down. Power supply current can be shut down (typ. 1μA) by stopping clocks and setting PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0569-E- [AK5700] 2006/12 ...

Page 60

... Note) The exposed pad on the bottom surface of the package must be open or connected to the ground. Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0569-E-01 PACKAGE 2.4 ± 0. Exposed Pad 7 6 0.23 ± 0.05 Epoxy Cu Solder (Pb free) plate - 60 - [AK5700 0.40 ± 0.1 1 PIN #1 ID 0.10 M (0. 2006/12 ...

Page 61

... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0569-E-01 MARKING 5700 XXXX 1 XXXX : Date code identifier (4 digits) Revision History Page Contents 40 Register Map (Addr=17H) Bit (D0) value was changed: 0 → 1 IMPORTANT NOTICE - 61 - [AK5700] 2006/12 ...

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