ak5367a AKM Semiconductor, Inc., ak5367a Datasheet

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ak5367a

Manufacturer Part Number
ak5367a
Description
96khz 24-bit ?? Adc With 0v Bias Selector
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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AK5367A is a high-performance 24-bit, 96kHz sampling ADC for consumer audio and digital recording
applications. The AK5367A uses an Enhanced Dual-Bit modulator architecture, this analog-to-digital
converter has an impressive dynamic range of 102dB with high level integration. The AK5367A has a
4-channel stereo input selector, an input Programmable Gain Amplifier with resistance. All this integration
with high-performance makes the AK5367A well suited for CD and DVD recording systems. The
integrated charge pump circuit can generate the negative power supply and remove the output coupling
capacitor.
MS0967-E-00
1. 24bit Stereo ADC
2. Control Interface: I
3. Master Mode / Slave Mode
4. Master Clock:
5. Sampling Rate: 32kHz to 96kHz
6. Power Supply
7. Ta = −20 ∼ 85°C
8. Package: 30pin VSOP
• 4:1 0V Bias Stereo input Selector
• Digital HPF for offset cancellation (fc=1.0Hz@fs=48kHz)
• Decimation LPF: -0.2dB@ 20kHz, -3.0dB@23kHz (fs=48kHz)
• Soft Mute
• Single-end Inputs
• S/(N+D): 90dB
• DR, S/N: 102dB
• Audio I/F Format: 24bit MSB justified, I
• Analog Supply: 4.5 ∼ 5.5V
• Digital Supply: 3.0 ∼ 3.6V
• 256fs/384fs (32kHz ∼ 96kHz)
• 512fs/768fs (32kHz ∼ 48kHz)
2
C-Bus
96kHz 24-Bit ΔΣ ADC with 0V Bias Selector
GENERAL DESCRIPTION
= Preliminary =
FEATURES
- 1 -
2
S
AK5367A
[AK5367A]
2008/05

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ak5367a Summary of contents

Page 1

... AK5367A is a high-performance 24-bit, 96kHz sampling ADC for consumer audio and digital recording applications. The AK5367A uses an Enhanced Dual-Bit modulator architecture, this analog-to-digital converter has an impressive dynamic range of 102dB with high level integration. The AK5367A has a 4-channel stereo input selector, an input Programmable Gain Amplifier with resistance. All this integration with high-performance makes the AK5367A well suited for CD and DVD recording systems ...

Page 2

... ROPIN ROUT MS0967-E-00 24K 10μ + LISEL PDN HPF ADC 0V 1Vrms ADC HPF Charge Pump RISEL 10μ 24K 0.1μ Figure 1. AK5367A Block Diagram - 2 - AVDD VSS1 DVDD VCOM ADC LRCK Audio BICK I/F SDTO MCLK SCL SDA CVEE VSS2 CVDD 1μ [AK5367A] 2008/05 ...

Page 3

... RIN1 3 LIN2 4 RIN2 5 LIN3 6 RIN3 7 LIN4 8 RIN4 9 RISEL 10 ROUT 11 ROPIN 12 LOPIN 13 LOUT 14 LISEL 15 MS0967-E-00 −20 ∼ +85°C 30pin VSOP (0.65mm pitch) Evaluation Board for AK5367A AK5367AEF Top View - 3 - [AK5367A] 30 AVDD 29 VSS1 28 DVDD 27 LRCK 26 MCLK 25 BICK 24 SDTO SCL 23 SDA 22 PDN ...

Page 4

... CP pin. Non polarity capacitors can also be used. Power Down Mode & Reset Pin “H”: Power up, “L”: Power down & Reset The AK5367A must be reset once upon power-up. Control Data Input / Output Pin Control Data Clock Pin in I ...

Page 5

... Pin Name LIN1-4,RIN1-4,LISEL,RISEL Analog LOPIN,LOUT,ROPIN,ROUT MS0967-E-00 Channel Clock Pin “L” Output in Master Mode at PWN bit= “0”. Digital Power Supply Pin, 3.0∼ 3.6V Analog Ground Pin Analog Power Supply Pin, 4.5 ∼ 5.5V These pins must be open Function Setting [AK5367A] 2008/05 ...

Page 6

... In slave mode, the AK5367A must be power up at the PDN pin = “L”. In master mode, the AK5367A must be power up at the PDN pin = “L”, or when DVDD is powered up, MCLK clock must input and the AK5367A must be reset by the PDN pin=“L”. The internal register data is unknown until PDN pin=“ ...

Page 7

... L include the feedback resistor (Rf) and the input impedance of the LISEL/RISEL pins. The value of C include the internal impedance of the AK5367A. Note 7. This value is measured via the following path. Pre-Amp → ADC.(Ri= 47kΩ, Rf= 24 kΩ) Note 8. Input voltage to LISEL and RISEL pins is proportional to AVDD voltage. typ. Vin = 0.6 x AVDD (Vpp) Note 9 ...

Page 8

... MS0967-E- C1=10μF LISEL LOPIN LOUT R i LIN1 R i LIN2 - + R i LIN3 LIN4 AK5367A Figure 2. Pre-Amp Circuit - 8 - [AK5367A ADC 2008/05 ...

Page 9

... VOH DVDD−0.5 VOL VOL Iin - 9 - typ max 18.9 20.0 - 23.0 - ±0. 1.0 6.5 typ max 37.8 40.0 - 46.0 - ±0. 2.0 13.0 min typ max - - - - 30%DVDD - - - - 0 0.4 ± [AK5367A] Units kHz kHz kHz kHz dB dB μs 1/ Units kHz kHz kHz kHz dB dB μs 1/ Units μA 2008/05 ...

Page 10

... [AK5367A] typ max Units 24.576 MHz ns ns 36.864 MHz kHz 64fs 400 kHz μ ...

Page 11

... PDN “↑” to SDTO valid at Slave Mode PDN “↑” to SDTO valid at Master Mode Note 16. The AK5367A can be reset by bringing the PDN pin = “L”. Note 17. This cycle is the number of LRCK rising edges from the PDN pin = “H”. ...

Page 12

... Timing Diagram MCLK LRCK BICK LRCK tSHLR BICK tLRS SDTO MS0967-E-00 1/fCLK tCLKH tCLKL 1/fs tSCK tSCKH tSCKL Figure 3. Clock Timing tLRSH tSSD Figure 4. Audio Interface Timing (Slave mode [AK5367A] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD 2008/05 ...

Page 13

... Figure 5. Audio Interface Timing (Master mode) tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure Bus mode Timing tPDV tPD Figure 7. Power Down & Reset Timing - 13 - [AK5367A] 50%DVDD dSCK 50%DVDD 50%DVDD VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL 50%DVDD VIL ...

Page 14

... In slave mode, all external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = “L”. If these clocks are not provided, the AK5367A may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5367A in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless the PDN pin = “ ...

Page 15

... Master Mode and Slave Mode The AK5367A becomes slave mode when the power-down mode (PDN pin = “L”) or exiting power-down. After exiting the power-down mode, master mode should be set by CKS2-0 bits. In master mode, LRCK and BICK pins are floating until CKS2-0 bits fixed. Therefore BICK and LRCK pins must be connected with 100 kΩ ...

Page 16

... Power-down The AK5367A is placed in the power-down mode by bringing the PDN pin = “L” and the digital filter is also reset at the same time. This reset must always be executed after power-up. At the power-down mode, the VCOM voltage is VSS1. After exiting the power-down mode, the Charge pump circuit is powered up, then Pre-Amp circuit is automatically powered up and an analog initialization cycle 4388 x LRCK cycles at slave mode, and 4385 x LRCK cycles in master mode ...

Page 17

... System Reset The AK5367A must be reset once by bringing the PDN pin “L” after power-up. At the slave mode, the internal timing starts clocking by the rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK. The AK5367A is in power-down states until the LRCK is input. At master mode, bringing the PDN pin “H” and exiting from reset and power down state by MCLK input. ■ ...

Page 18

... The output signal is attenuated by −∞ within 1024 LRCK cycles (1024/fs). (2) When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms because there is some DC difference between the channels. MS0967-E-00 (1) (2) -∞ LIN 1 [AK5367A] (Figure 12). (1) LIN 2 2008/05 ...

Page 19

... Pre-Amp RIN3 RIN4 ROPIN ROUT Rf C1=10μF Figure 13. Pre-Amp and Input ATT ATT Gain [dB] Rf [kΩ Table 5. Input ATT example - 19 - [AK5367A] Table 5 shows the example of Ri and Rf. LISEL ADC ADC RISEL LISEL/RISEL pin −11.86 1.02Vrms −5.84 1.02Vrms 0 1Vrms 2008/05 ...

Page 20

... Charge Pump Circuit The internal charge pump circuit generates negative voltage(CVEE) from CVDD voltage. The generated voltage is used for Pre-Amp. CVDD MS0967-E-00 AK5367A To Pre-Amp Charge Negative Voltage Pump CVEE CP CN VSS2 Cp=0.1μF Cout=1μF Figure 14. Charge Pump Circuit - 20 - [AK5367A] 2008/05 ...

Page 21

... This address is 7 bits long followed by the eighth bit that is a data direction bit (R/W). The most significant 7 bits of the slave address are fixed as “0110001”. If the slave address matches that of the AK5367A, the AK5367A generates an acknowledge and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse R/W bit value of “ ...

Page 22

... READ Operations Set the R/W bit = “1” for the READ operation of the AK5367A. The master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. After receiving each data packet the internal 2-bit address counter is incremented by one, and the next data is automatically taken into the next address. If the address exceeds 02H prior to generating a stop condition, the address counter will “ ...

Page 23

... SCL FROM MASTER S START CONDITION SDA SCL MS0967-E-00 Figure 21. START and STOP Conditions Figure 22. Acknowledge on the I data line change stable; of data data valid allowed 2 Figure 23. Bit Transfer on the I C-Bus - 23 - [AK5367A] P stop condition not acknowledge acknowledge 8 clock pulse for acknowledgement C-Bus 9 2008/05 ...

Page 24

... SEL2 SEL1 DIF CKS2 CKS1 CKS0 SEL2 SEL1 R CKS2 CKS1 CKS0 R/W R/W R [AK5367A] D0 PWN SEL0 SMUTE D0 PWN R SEL0 R SMUTE R/W 0 2008/05 ...

Page 25

... BICK 25 AK5367A 7 RIN3 SDTO 24 8 LIN4 SCL 23 RIN4 9 SDA 22 10 RISEL PDN 21 ROUT ROPIN LOPIN CVDD 18 LOUT 14 VSS2 17 LISEL 15 CVEE 16 Figure 24. Typical Connection Diagram - 25 - [AK5367A] + 0.1u 2.2u Analog 5V + 0.1u 10u 0.1u Digital 3.3V + 10u DSP or μP Digital 3.3V + 0.1u Analog Digital + Ground Ground 0.1u 10u + 1u 2008/05 ...

Page 26

... VSS1 and VSS2 of the AK5367A must be connected to analog ground plane. System analog ground and digital ground must be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors must be as near to the AK5367A as possible, with the small value ceramic capacitor being the closest. ...

Page 27

... VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0967-E-00 PACKAGE 16 15 0.65 Detail A 0.08 Epoxy Cu Solder (Pb free) plate - 27 - [AK5367A] 1.5MAX A +0.10 0.15 -0.05 2008/05 ...

Page 28

... MS0967-E-00 MARKING AKM AK5367AEF XXXBYYYYC XXXBYYYYC Date code identifier REVISION HISTORY Reason Page Contents First Edition MPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK5367A] in any safety, life support, or Note1) 2008/05 ...

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