ak5388 AKM Semiconductor, Inc., ak5388 Datasheet
ak5388
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ak5388 Summary of contents
Page 1
... The AK5388 achieves 120dB dynamic range and –105dB THD+N, and an optional mono mode extends dynamic range to 121dB. The AK5388’s digital filter features a modified FIR architecture that minimizes group delay while maintaining excellent linear phase response. ...
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... L Ordering Guide AK5388EQ –10 ~ +70 C AKD5388 Evaluation Board for AK5388 L Pin Layout VREFP2 34 VREFL2 35 VCOM2 36 LIN2+ 37 LIN2- 38 TEST3 39 RIN1- 40 RIN1+ 41 VCOM1 42 VREFL1 43 VREFP1 44 Rev. 0.3 44pin LQFP (0.8mm pitch) 22 TDM1 21 TDM0 20 TDMIN 19 OVF AK5388EQ 18 SDTO2 17 SDTO1 16 VSS3 Top View 15 DVDD 14 LRCK 13 BICK ...
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... Clock Mode Select #2 Pin 9 CKS2 I Power-Down Mode Pin 10 PDN I When “L”, the circuit is in power-down mode. The AK5388should always be reset upon power-up. Master/Slave mode Select Pin 11 M/SN I “L”: Slave mode, “H”: Master mode 12 MCLK I Master Clock Input Pin ...
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... Normally connected to AVSS1 with a 0.1 F ceramic capacitor in parallel with an electrolytic capacitor less than 2 VREFL1 I ADC1 Low Level Voltage Reference Input Pin 44 VREFP1 I ADC1 High Level Voltage Reference Input Pin Note: All digital input pins should not be left floating. Rev. 0.3 (Connected to VSS) 5.25V (Connected to VSS [AK5388] 2007/10 ...
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... These pins should be connected to AVSS. These pins should be connected to AVSS. These pins should be connected to AVDD. This pin should be open. This pin should be connected to DVSS. ABSOLUTE MAXIMUM RATINGS Symbol AVDD1/2 DVDD1 DVDD2 IIN VINA VIND Ta Tstg - 5 - [AK5388] min max Units 0.3 6.0 V 0.3 6.0 V 0.3 6 0.3 AVDD+0 ...
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... Vin (typ, @ 0dB) = 2.9 x {(VREF+) – (VREF–)} / 5 [V]. WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. Rev. 0.3 Symbol min AVDD1/2 4.75 DVDD 3.0 (Note 5) VREFP1/2 AVDD-0.5 (Note 6) VREFL1/2 VSS VREF AVDD-0 [AK5388] typ max Units 5.0 5.25 V 3.3 3 AVDD AVDD V 2007/10 ...
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... TBD 20dBFS - 60dBFS - 1dBFS TBD 20dBFS - 60dBFS - 1dBFS - 20dBFS - 60dBFS - Stereo Mode TBD Mono Mode - Stereo Mode TBD Mono Mode - TBD TBD (Note 9) (Note 10 [AK5388] typ max Units - 24 Bits 2.9 3.1 Vpp 105 - 102 - 102 - ...
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... DFS1 = “L”, DFS0 = “L”) Symbol min 27 12 3.6V; DFS1 = “L”, DFS0 = “H”) Symbol min 55 12 [AK5388] typ max Units 21.6 kHz 22.0 - kHz 23.8 - kHz 24.4 - kHz kHz 0. 12.6 1/fs 0.01 s 1.0 Hz 6.5 Hz typ max Units 43.3 kHz 44.2 - kHz 47 ...
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... Rev. 0.3 3.6V; DFS1 = “H”, DFS0 = “L”) Symbol min 141 12 CHARACTERISTICS 3.6V) Symbol min VIH 70%DVDD VIL - VOH DVDD 0.4 VOL - Iin - - 9 - [AK5388] typ max Units - - kHz 83.4 - kHz 99.9 - kHz 106.5 - kHz kHz 0. 9.8 1/ 1.0 Hz 6.5 Hz typ Max Units - - ...
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... Duty tLRH 1/256fs tLRL 1/256fs fs 8 tLRH 1/128fs tLRL 1/128fs fs 8 Duty fs 8 (Note 13) tLRH fs 8 (Note 13) tLRH - 10 - [AK5388] typ max Units 12.288 27.648 MHz ns ns 18.432 36.864 MHz ns ns 24.576 27.648 MHz ns ns 36.864 36.864 MHz ns ns 216 kHz 55 % ...
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... TBD (Note 15) tBSD TBD (Note 17) tPD 150 (Note 18) tPDV - 11 - [AK5388] typ max Units TBD ns 64fs ...
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... Note 15. SDTO2 output is fixed to “L”. Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs. Note 17. The AK5388 can be reset by bringing the PDN pin = “L”. Note 18. This cycle is the number of LRCK rising edges from the PDN pin = “H”. ...
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... Note: SDTO shows SDTO1 and SDTO2. LRCK tBLR BICK SDTO1 tTDMS TDMIN Figure 4. Audio Interface Timing (Slave mode, TDM0 pin = “H”) Rev. 0.3 tLRB tBSD tLRB tBSD - 13 - [AK5388] VIH VIL VIH VIL 50%DVDD VIH VIL VIH VIL 50%DVDD VIH VIL 2007/10 ...
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... Figure 5. Audio Interface Timing (Slave mode, TDM0 pin = “H” ,TDM1 pin = “H” ,8KHz LRCK tBLR BICK SDTO1 Figure 6. Audio Interface Timing (Slave mode, TDM0 pin = “H”,TDM1 pin = “H” ,108KHz < fs Rev. 0.3 tLRB tBSD tLRB tBSS tBSH DATA - 14 - [AK5388] VIH VIL VIH VIL 50%DVDD fs 108KHz) VIH VIL VIH VIL 50%DVDD 216KHz) ...
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... Note: SDTO shows SDTO1 and SDTO2. Rev. 0.3 dBCK tBSD tPDV Figure 8. Power Down & Reset Timing - 15 - [AK5388] 50%DVDD 50%DVDD 50%DVDD VIH VIL ...
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... AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5388 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be provided unless PDN pin = “L”. ...
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... When changing MCLK frequency in master/slave mode, the AK5388 should reset by PDN pin = “L”. (ex. 12.288MHz(@fs=48kHz) at CKS1 pin = CKS0 pin = “L”. L Audio Interface Format 12 different audio data interface formats can be selected using the TDM1-0, M/S and DIF pins as shown in audio data format can be selected by the DIF pin ...
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... Lch Data 2 256 BICK BICK 32 BICK 32 BICK - 18 - [AK5388] LRCK BICK I/O I/O H/L I 48-128fs I L/H I 48-128fs I H/L O 64fs O L/H O 64fs O I 256fs ...
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... BICK 32 BICK [AK5388 ...
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... L Power Down and Reset The AK5388 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog initialization cycle starts after exiting the power-down mode. The output data SDTO is valid after 516 cycles of LRCK clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are forced to “ ...
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... L Cascade TDM Mode The AK5388 supports cascading two devices in a daisy chain configuration in TDM256 mode. In this mode, SDTO2 pin of device #1 is connected to TDMIN pin of device #2. The SDTO1 pin of device #2 can output 8-chnnels of TDM data multiplexed with 4-chnnel of TDM data from device #1 and 4-channel of TDM data from device #2. ...
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... ASAHI KASEI L Mono mode When the MONO pin is set to “H”, the AK5388 is in MONO mode. In the Mono mode, dynamic range and S/N can be improved by approximately 3dB when the same analog signal is inputted to left and right channels. The output data format determined. ...
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... Note: - AVSS, BVSS and DVSS of the AK5388 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All input pins except pull-down (CKS0, CKS1 and TEST pin) pin should not be left floating. ...
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... System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5388 as possible, with the small value ceramic capacitor being the nearest. ...
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... The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is +/-TBDVpp (AK5388: +/-2.9Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=120dB, S/(N+D)=TBDdB. ...
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... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 0.30 10. 0.37 0.10 0.15 L Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: Rev. 0.3 PACKAGE 1.70max 0.60 0.20 Epoxy Cu Solder (Pb free) plate - 26 - [AK5388] 0 0.2 0.17 0.05 2007/10 ...
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... Rev. 0.3 MARKING AK5388EQ XXXXXXX AKM 1 1) Pin #1 indication 2) Audio 4 pro Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK5388 5) AKM Logo IMPORTANT NOTICE , and AKEMD assumes no responsibility for such use, except for the use Note2 [AK5388] in any safety, life support, or Note1) 2007/10 ...